Interconnect Structure for Stacked Semiconductor Wafers
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller form factors, higher integration density, and lower power consumption as demand increases for miniaturization, higher speed, and greater bandwidth, particularly in stacked semiconductor devices where effective interconnect structures are needed to connect dies efficiently.
Innovation Solution
The development of an interconnect structure that involves forming metal pads on semiconductor wafers, bonding them using direct bonding techniques, and creating conductive plugs through a series of etching and deposition processes to establish electrical connections between the wafers, reducing parasitic capacitance and power consumption while maintaining a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If direct bonding techniques are used to bond semiconductor wafers, then integration density and form factor are improved, but parasitic capacitance increases and power consumption increases
Solution Approach 1:
A dielectric layer is introduced as an intermediary material between the bonded semiconductor wafers. This dielectric layer replaces direct metal-to-metal contact with metal-to-dielectric-to-metal connections, thereby reducing parasitic capacitance while maintaining the bonded wafer structure for high integration density
Solution Approach 2:
The interconnect structure is segmented into multiple components: metal pads on each wafer, a dielectric layer in between, and conductive plugs connecting them. This segmentation allows optimization of each component's properties, particularly using the dielectric layer to reduce capacitance while maintaining electrical connectivity
2Volume of moving object
If direct bonding techniques are used to bond semiconductor wafers, then form factor is reduced, but power consumption increases
Solution Approach 1:
The dielectric layer serves as a mediator that reduces capacitive coupling between adjacent interconnects in the stacked wafer structure. By lowering parasitic capacitance, the energy required for signal transmission is reduced, thereby decreasing power consumption while maintaining the compact stacked form factor
Solution Approach 2:
The dielectric material properties are optimized to achieve low capacitance values. By selecting and engineering dielectric materials with appropriate permittivity and thickness, the parasitic capacitance is minimized, reducing power consumption in the compact stacked device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables higher integration density, reduced form factor, cost-effectiveness, and lower power consumption by establishing efficient electrical connections between stacked semiconductor wafers, enhancing performance and reducing interference.
Implementation Method 1
Two semiconductor wafers may be bonded together through suitable bonding techniques. The commonly used bonding techniques include direct bonding
Data Source
AI summary
A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.