Interconnect Structure With Straight Sidewalls for Lower RC Delay
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Solution Overview
Problem
As semiconductor industry advances, the high aspect ratio of conductive features in dielectric material in BEOL interconnect structures leads to tapered sidewalls, worsening resistive-capacitive (RC) delay due to limitations in photo-lithographic definition and interconnect structure design.
Innovation Solution
The development of an interconnect structure with substantially straight sidewalls achieved through a dual-frequency plasma etching process, forming low-k dielectric layers with specific etch stop and oxide layers, and patterning techniques that reduce the number of processes and complexity, allowing for improved electrical isolation and reduced RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photo-lithographic definition is used to define conductive features, then the structure can be manufactured with conventional processes, but the sidewalls become tapered due to high aspect ratio, worsening RC delay
Solution Approach 1:
A sacrificial layer is introduced as an intermediary element between the dielectric material and the conductive features. This sacrificial layer enables the formation of openings with substantially straight sidewalls by serving as a template during the etching process, thereby improving manufacturing precision without directly compromising reliability
Solution Approach 2:
The sacrificial layer is formed in advance before creating the openings for conductive features. This preliminary action allows the openings to be defined with straight sidewalls from the outset, preventing the tapered sidewall formation that would otherwise worsen RC delay
2Productivity
If the number of manufacturing processes is reduced, then manufacturing efficiency improves, but achieving straight sidewalls with high aspect ratio becomes more difficult
Solution Approach 1:
Multiple functions are merged into the sacrificial layer formation step: it serves as both a structural template for defining opening geometry and as a sacrificial element that is later removed. This consolidation allows straight sidewalls to be achieved without adding significant process complexity, maintaining manufacturing efficiency while improving precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved RC delay performance and simplifies the manufacturing process by maintaining straight sidewalls and reducing the number of necessary steps, enhancing the overall efficiency of interconnect formation.
Implementation Method 1
dual-frequency plasma etching process
Data Source
AI summary
An interconnect structure, along with methods of forming such, are described. In some embodiments, the method includes forming a first dielectric layer over one or more devices, forming a first conductive feature in the first dielectric layer, and forming two dielectric features over the first dielectric layer and the first conductive feature. At least one of the two dielectric features has a first width, and each dielectric feature includes a first low-k dielectric layer, an oxide layer, and a first etch stop layer. The method further includes forming a second conductive feature between the two dielectric features, and the second conductive feature has a second width substantially the same as the first width.