Interconnect Structure Stress Adjustment Layer for Metal Silicide Contact Resistance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices integrate and linewidths decrease, contact resistance between electrodes and interconnects increases, leading to greater resistance-capacitance delay and reduced operating speed, necessitating a method to further reduce contact resistance in metal silicide structures.

Innovation Solution

A manufacturing method for an interconnect structure involving the formation of a dielectric layer, a metal layer, a stress adjustment layer, and a thermal process to form a metal silicide layer, where the stress adjustment layer is used to adjust substrate stress and increase the thickness of the metal silicide layer, thereby reducing contact resistance and enhancing on-current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the integration of semiconductor device increases and linewidth is reduced, then device integration density is improved, but contact resistance between electrodes and interconnects increases

Engineering Contradiction:
Improvedevice integration densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies parameter changes by modifying the physical and chemical properties of the metal silicide layer through controlled thermal processes. Specifically, the annealing temperature and duration are optimized to transform the metal layer into metal silicide with desired electrical properties, achieving lower contact resistance while maintaining high integration density

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses composite materials by forming metal silicide (a compound of metal and silicon) through the reaction between deposited metal layer and the silicon substrate. This composite structure combines the low resistance properties of metal with the semiconductor properties of silicon, optimizing both conductivity and device integration

Inventive Principle:
Principle #40Composite materials

2Reliability

If metal silicide is used to reduce contact resistance, then electrical conductivity is improved, but further reduction of contact resistance becomes increasingly difficult

Engineering Contradiction:
Improvecontact resistanceVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by depositing a metal layer before the thermal annealing process to form metal silicide in-situ. This preliminary metal deposition prepares the structure in advance, enabling the subsequent thermal process to directly form the low-resistance metal silicide contact without requiring additional post-processing steps

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs self-service through self-aligned metal silicide formation where the metal layer automatically reacts with the underlying silicon during thermal processing to form metal silicide. This self-aligned approach eliminates the need for separate patterning and deposition steps, reducing process complexity while achieving low contact resistance

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method results in a metal silicide layer with lower contact resistance and higher on-current, improving the operating speed of semiconductor devices by effectively managing substrate stress and layer thickness.

Implementation Method 1

A thermal process is performed to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer

Methodology Applied
Scientific EffectSolid-state diffusion: Diffusion

Implementation Method 2

the stress adjustment layer is used to adjust substrate stress and increase the thickness of the metal silicide layer

Methodology Applied
Scientific EffectMechanical stress: Stress Relaxation

Data Source

PatentUS10497607B2Manufacturing method of interconnect structure
Publication Date: 2019.12.03 UNITED MICROELECTRONICS CORP
  • US10497607B2 patent drawing
  • US10497607B2 patent drawing
  • US10497607B2 patent drawing

AI summary

A manufacturing method of an interconnect structure including the following steps is provided. A dielectric layer is formed on a silicon layer, wherein an opening exposing the silicon layer is in the dielectric layer. A metal layer is formed on the surface of the opening. A stress adjustment layer is formed on the metal layer. A thermal process is performed to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer. The stress adjustment layer is removed after the thermal process is performed. A barrier layer is formed on the surface of the opening.