Interconnect Substrate Filler Pattern Identification Without Marking Space

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Solution Overview

Problem

Existing interconnect substrates require additional size for identification marks, leading to increased substrate size and complexity, making it challenging to create a compact version with embedded identification information.

Innovation Solution

An interconnect substrate comprising an insulating layer, a dispersion layer with unique filler patterns, and an interconnect layer, where the dispersion layer includes non-conductive fillers dispersed in a main material, forming identifiable patterns via image recognition, allowing for compact design and accurate identification without additional space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If identification marks are formed on the insulator at the boundary of each piece, then positional information can be determined, but the substrate size increases due to required marking spaces

Engineering Contradiction:
Improveidentification accuracyVSAvoidsubstrate size
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The identification mark function is merged with the existing insulator material by dispersing fillers within it. This eliminates the need for separate marking spaces while maintaining identification capability, thereby reducing substrate size without sacrificing identification accuracy

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The insulator is given non-uniform local quality through selective filler dispersion. Areas with different filler concentrations or patterns provide identification information, allowing the substrate to carry identification data within its existing structure rather than requiring additional dedicated marking areas

Inventive Principle:
Principle #3Local quality

2Measurement precision

If identification marks are accurately embedded at predetermined positions, then identification is possible, but the device complexity increases due to additional marking processes

Engineering Contradiction:
Improveidentification accuracyVSAvoidmarking process complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The identification marking function is combined with the insulator fabrication process itself. By incorporating fillers into the insulator material during its formation, the identification pattern is created as an integral part of the manufacturing process rather than as a separate post-processing step, thereby reducing overall process complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The identification pattern is prepared in advance by dispersing fillers within the insulator material during its formation. This preliminary incorporation of identification features eliminates the need for subsequent complex marking operations, simplifying the overall manufacturing process while ensuring accurate identification

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240006334A1Interconnect substrate, method of making the same, and method of identifying interconnect substrate
Publication Date: 2024.01.04 SHINKO ELECTRIC IND CO LTD
  • US20240006334A1 patent drawing
  • US20240006334A1 patent drawing
  • US20240006334A1 patent drawing

AI summary

An interconnect substrate includes an insulating layer, a dispersion layer, and an interconnect layer, the insulating layer, the dispersion layer, and the interconnect layer being laminated together, wherein the dispersion layer includes a main material and one or more fillers dispersed in the main material, the one or more fillers forming a unique dispersion pattern, and wherein the unique dispersion pattern is identifiable by image recognition from outside of the interconnect substrate.