Interconnect Substrate Recess Curvature for Gap-Free Plating
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Solution Overview
Problem
Existing interconnect substrates face issues with connection reliability between interconnect layers due to gaps formed in recesses during the plating process, which compromises the integrity of the electrical connections.
Innovation Solution
The formation of a recess on the interconnect layer surface with a specific curvature and the use of adhesion enhancing films, such as silane coupling agents, to ensure complete filling of the recess with the plating layer, thereby preventing gaps and enhancing adhesion between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a recess is formed on the interconnect layer surface during via hole creation, then adhesion between interconnect layers is improved, but gaps may form in the recess during plating process
Solution Approach 1:
The recess surface is designed with a specific curved profile characterized by controlled curvature radii. The curvature radius at the recess bottom is larger than at the opening, creating a smooth过渡 that prevents capillary action from trapping air bubbles during plating. This curvature control ensures complete metal filling without gaps while maintaining the adhesion benefits of the recess structure.
Solution Approach 2:
The invention controls specific geometric parameters of the recess including depth, opening diameter, and curvature radius. By optimizing these parameters, the recess provides sufficient surface area for adhesion enhancement while maintaining a profile that allows complete plating solution penetration and bubble-free filling, thus improving connection reliability without creating gap defects.
2Reliability
If adhesion enhancing films are applied to the interconnect layer, then adhesion between layers is enhanced, but the plating process becomes more complex
Solution Approach 1:
The invention combines the adhesion enhancing film application with the existing via hole formation and plating processes. The recess structure is formed as part of the via hole creation process, and the adhesion film is applied to both the interconnect layer surface and the recess walls before plating. This integrated approach enhances adhesion without requiring separate complex process steps.
3Manufacturing precision
If the recess has a large opening area to improve filling, then plating solution can penetrate better, but the recess depth-to-area ratio decreases affecting adhesion
Solution Approach 1:
The controlled curvature profile with a larger radius at the bottom and smaller radius at the opening creates an optimized surface area distribution. This curvature design ensures that the plating solution can effectively wet and fill the recess while the total surface area (including the curved walls) remains sufficient for strong adhesion between the interconnect layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the connection reliability by ensuring the plating solution effectively fills the recess, reducing the likelihood of gaps and enhancing the adhesion between interconnect layers, thus stabilizing electrical connections.
Implementation Method 1
the plating solution effectively fills the recess
Implementation Method 2
adhesion enhancing films, such as silane coupling agents, to ensure complete filling of the recess with the plating layer, thereby preventing gaps and enhancing adhesion between layers
Data Source
AI summary
An interconnect substrate includes a first interconnect layer having a first surface in which a recess is formed, an insulating layer that has a second surface facing the first surface and covers the first interconnect layer, a via hole overlapping the first interconnect layer in plan view and penetrating the insulating layer, and a second interconnect layer formed on the insulating layer and situated in contact with the first interconnect layer through the via hole.