Inter-processor communication via task register and interconnect
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated-circuit devices with multiple processing units face security concerns and timing issues due to bridges between local buses, which can allow malicious or faulty software to interfere with other processing units, and may experience timing issues even with bridges present.
Innovation Solution
A novel mechanism for inter-processor communication using a first and second processing subsystem with a bridge unit and an electrical interconnect, allowing a processor or peripheral to interrupt another processor by writing to a task register, without requiring a bridge between local buses, and enabling power domain management for wake-up signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a bridge is provided between local buses of different processing units, then inter-processor communication is enabled, but security concerns arise allowing unrestricted access to memory maps
Solution Approach 1:
The patent introduces an electrical interconnect as an intermediary mechanism between processing units, replacing direct bridge connections. This interconnect uses defined event signals and task registers to mediate communication, allowing processors to interact only through controlled interfaces rather than direct bus access, thus maintaining security while enabling communication.
Solution Approach 2:
The patent segments the communication mechanism into distinct components: event signals for notification, task registers for data transfer, and local event lines for peripheral interaction. This segmentation allows each component to have specific access controls and functions, preventing unauthorized access to entire memory maps while enabling targeted communication.
2Ease of operation
If a bridge is provided between local buses, then inter-processor communication is enabled, but timing issues may occur
Solution Approach 1:
The electrical interconnect acts as a dedicated timing mechanism between processors, using synchronized event signals that eliminate the timing uncertainties associated with bridge-based communication. The interconnect provides predictable signal propagation paths with known latency characteristics.
3Adaptability or versatility
If the task register is made accessible over the second local bus, then more processors can access it, but security is compromised
Solution Approach 1:
The patent applies local quality by making the task register accessible only to specific processing units through the electrical interconnect rather than universally over the local bus. Each processor has defined access rights to specific task registers through the interconnect, providing localized accessibility that maintains security while enabling necessary communication.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor integrated-circuit device (1; 201) comprises two processing subsystems (10, 40; 210, 240), each comprising a respective processor(14, 44; 214; 244), set of local peripherals(16, 46; 216; 246),andbridge unit(22, 52; 222, 252), all connected to a respective local bus(12, 42; 212, 242).An electrical interconnect (70; 270) joins the respective bridge units.The first bridge unit(22; 222)comprises a task register(24a), accessible over the first local bus(12), and can be configured to detect a write to the task register(24a),andrespond by sending an event signal over the interconnect (70; 270) to the second bridge unit(52; 252).The second bridge unit (52; 252) can be configured to receive the event signal, and respond by sending an interrupt signal to the second processor(44; 244).