Two-Step Interconnect Testing Using Diode Deviation Paths
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Solution Overview
Problem
The challenge in testing interconnects within semiconductor dies, particularly in three-dimensional stacked ICs, lies in accessing both ends of the interconnects for conventional testing, which is difficult due to the fine-pitched microbumps and the need for dual-side probing on thinned wafers, leading to deformation issues and high costs associated with faulty interposers being detected only after stacking.
Innovation Solution
A method that allows for two-step testing of interconnects using an electrical component as a deviation path, enabling testing from one end of the interconnect to the component and then from the other end, eliminating the need for simultaneous physical probe access at both ends, and utilizing diodes for ESD protection and testing, which can be reused for interconnect testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used requiring dual-side probing, then complete interconnect testing can be achieved, but wafer deformation occurs and access becomes difficult
Solution Approach 1:
The patent introduces an electrical component (such as a diode) as an intermediary element that provides a deviation path for test signals. This intermediary allows testing of the interconnect from one side by routing the signal through the component, eliminating the need for simultaneous dual-side probe access while maintaining testing completeness
Solution Approach 2:
The patent adds a temporal dimension to the testing process by implementing a two-step testing sequence. Instead of requiring simultaneous access to both ends (spatial dimension), the test is performed in two sequential steps from one side, using the electrical component to enable signal routing back through the interconnect
2Ease of manufacture
If pre-bond testing of interposer is performed, then cost of faulty interposers is reduced, but test access complexity increases
Solution Approach 1:
The patent makes existing electrical components (diodes for ESD protection) serve dual functions: their original protection function and a new testing function. By utilizing the deviation path through these existing components, the patent enables testing without adding separate test-access structures, thus reducing overall device complexity
Solution Approach 2:
The electrical components already present in the interposer (designed for ESD protection) are made to serve the additional purpose of providing test signal routing. The structure essentially tests itself by utilizing its own existing components rather than requiring external test-access infrastructure
3Productivity
If microbumps with fine pitch are used for interconnection, then functionality increases, but probe card cost and accuracy deteriorate
Solution Approach 1:
The patent extracts the testing function from the microbump interconnect structure itself and relocates it to larger, more accessible electrical components (diodes). By taking out the testing requirement from the fine-pitch microbump region and moving it to coarser-pitch component locations, the patent eliminates the need for expensive high-precision probe cards
Data Source
AI summary
A method is provided for testing an interconnect (32) in a semiconductor die (30), the semiconductor die (30) having at its surface a plurality of electrical contact elements (Pad A, Pad B, Pad X, Pad Y), and comprising at least an interconnect-under-test (32) between a first electrical contact element (Pad A) and a second electrical contact element (Pad B), there being an electrical component (C) electrically coupled between the interconnect-under-test (32) and at least one third electrical contact element (Pad X, Pad Y). The method comprises testing a first signal path in the semiconductor die (30) for manufacturing defects, the first signal path comprising a first part of the interconnect-under-test (32) and a first deviation path from the interconnect-under-test (32) over the electrical component (C) to a third electrical contact element (Pad X), thus obtaining first test results; and testing a second signal path in the semiconductor die (30) for manufacturing defects, the second signal path comprising a second part of the interconnect-under-test (32) and a second deviation path from the interconnect-under-test (32) over the electrical component (C) to a third electrical contact element (Pad Y), thus obtaining second test results. The first and the second part of the interconnect-under-test together form the interconnect-under-test (32).