Semiconductor Interconnect Structure With Thin Ru Line Over Via
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Solution Overview
Problem
The scaling down of integrated circuit (IC) feature sizes has led to increased complexity and challenges in forming copper-based interconnect structures, including higher aspect ratios, resistivity, and line-to-line capacitance, resulting in issues such as voids, collapse, and damage to surrounding layers during patterning and deposition processes.
Innovation Solution
The method involves directly depositing conductive materials over vias to form conductive lines with a reduced thickness, thereby lowering the aspect ratio of interconnect features, and using materials like Ru and Co with lower resistivity than copper to reduce capacitance and electron scattering, bypassing the need for patterning through ILD layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If copper-based interconnect structures are used in multilayer interconnect features with shrinking IC feature size, then production efficiency is improved and costs are lowered, but the interconnect structures exhibit higher aspect ratios, resistivity, and line-to-line capacitance, and cause damages in surrounding ILD layers
Solution Approach 1:
The patent changes the material parameter from copper to ruthenium and cobalt, which have different physical and chemical properties including lower resistivity and better adhesion characteristics, thereby resolving the reliability issues while maintaining productivity
Solution Approach 2:
The patent introduces a barrier layer as an intermediary between the conductive material and the ILD layer, preventing direct interaction and damage between copper and the surrounding dielectric material, thus protecting the ILD layer from damage
2Area of moving object
If copper-based interconnect structures are formed with ever-shrinking IC feature size, then functional density is increased, but voids, collapse, and bend develop during patterning and deposition processes
Solution Approach 1:
The patent changes the material composition to ruthenium and cobalt, which have superior mechanical properties and adhesion characteristics, preventing void formation, collapse, and bend during the patterning and deposition processes while enabling smaller feature sizes
Solution Approach 2:
The patent applies a barrier layer treatment before depositing the conductive material, preparing the surface in advance to prevent adhesion issues and structural defects that would lead to voids and collapse during subsequent processing
3Ease of manufacture
If conventional patterning through ILD layers is used, then conductive lines can be formed, but damage from etchant gases occurs to surrounding layers
Solution Approach 1:
The patent uses the barrier layer as a protective intermediary that shields the ILD layer and surrounding structures from etchant gas exposure during patterning, preventing damage while allowing the conductive line formation process to proceed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach mitigates issues like void formation and line distortion, reduces capacitance, and minimizes damage from etchant gases, leading to improved electrical performance and structural integrity of IC devices.
Implementation Method 1
using materials like Ru and Co with lower resistivity than copper to reduce capacitance and electron scattering
Implementation Method 2
directly depositing conductive materials over vias to form conductive lines
Data Source
AI summary
A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via.