Interconnect Timing Analysis Using Capacitance Resistance Dominance
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Solution Overview
Problem
Current methods for simulating signal propagation delays in integrated circuits are inaccurate due to correlations between resistance and capacitance variations, leading to misleading results when determining minimum and maximum propagation times, which can cause timing failures in circuit designs.
Innovation Solution
Estimate minimum and maximum signal propagation delay values for each interconnect by determining whether the delay is dominated more by capacitance or the capacitance and resistance product term, using a factor k to adjust parameter values for calculations, and considering different process variation cases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the entire design is analyzed using 'best case' capacitances, then the capacitance value is optimized, but the propagation delay assessment becomes inaccurate due to correlation between resistance and capacitance variations
Solution Approach 1:
The patent segments the interconnect into multiple sections and analyzes each section's resistance and capacitance variations separately. By dividing the overall propagation delay into segment contributions, the method can identify which segments dominate the delay and apply appropriate best-case or worst-case assumptions only to those critical segments, rather than uniformly applying assumptions to the entire design.
Solution Approach 2:
The patent dynamically changes the capacitance parameter assumptions based on the calculated resistance value and driving strength. When resistance is low and driving strength is high, the method switches to using best-case capacitance values. When resistance is high or driving strength is low, it uses worst-case capacitance values. This conditional parameter adjustment resolves the contradiction by adapting the analysis approach to the specific electrical characteristics of each interconnect.
2Ease of operation
If uniform best-case or worst-case assumptions are applied to all interconnects, then the analysis is simplified, but the correlation between resistance and capacitance variations is ignored leading to misleading results
Solution Approach 1:
The patent introduces dynamic decision-making into the timing analysis by evaluating the driving strength and resistance characteristics of each interconnect and automatically selecting the appropriate analysis mode (best-case, worst-case, or nominal). This dynamic approach maintains ease of operation through automated selection while improving precision by adapting to the specific electrical conditions of each interconnect segment.
3Measurement precision
If the interconnect is segmented into multiple sections, then the propagation delay can be more accurately attributed to specific segments, but the device complexity increases
Solution Approach 1:
The patent segments the interconnect into multiple sections to identify which segments contribute most to the overall propagation delay. By calculating the resistance and capacitance of each segment separately, the method can attribute delay contributions accurately and apply best-case or worst-case assumptions only where necessary, improving precision while managing complexity through targeted analysis.
Solution Approach 2:
The patent applies partial analysis by focusing computational effort only on interconnect segments that significantly contribute to propagation delay. Rather than performing exhaustive analysis on all segments with equal detail, the method identifies critical segments and applies detailed segment-level analysis only where needed, reducing overall complexity while maintaining necessary precision.
Data Source
AI summary
Roughly described, signal propagation delay values are estimated for a plurality of interconnects in a circuit design. For each interconnect, the propagation delay value(s) are estimated in dependence upon a preliminary approximate determination of whether the signal propagation delay is dominated more by an interconnect capacitance term or by an interconnect capacitance and resistance product term. If it is dominated more by the interconnect capacitance term, then the parameter values used for a minimum propagation delay calculation are obtained assuming a smallest capacitance process variation case and the parameter values used for a maximum propagation delay calculation are obtained assuming a largest capacitance process variation case. If the signal propagation delay is dominated more by the interconnect capacitance and resistance product term, then the opposite assumptions are made. Preferably the approximate determination is made by comparing Rint to k*Rd.