On-Chip Interconnect Timing Calibration for Wire Delay Mismatch
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Solution Overview
Problem
On-chip source-synchronous, CMOS-repeater-based interconnects face significant challenges due to wire delay mismatches, timing jitter, and power supply noise, leading to severe yield loss and functional failures in high-speed data transmission.
Innovation Solution
A timing calibration technique that applies transition patterns to calibrate and trim the delays of clock and data wires using a configurable delay circuit, reducing wire delay mismatches and improving chip yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If wire length is increased to support larger silicon die sizes, then communication coverage is improved, but wire delay mismatch increases
Solution Approach 1:
The patent applies timing calibration before normal operation to compensate for wire delay mismatches. Transition patterns are transmitted through the interconnect, delay measurements are taken, and delay trim values are calculated and stored in a lookup table before actual data transmission begins. This preliminary calibration action resolves the delay mismatch problem that arises from long wire lengths needed for large die sizes.
2Productivity
If clock frequency is increased to improve performance, then productivity is improved, but timing margin decreases
Solution Approach 1:
The patent implements a feedback mechanism where delay measurements from transmitted transition patterns are used to calculate delay trim values. These trim values are stored in a lookup table and applied during normal operation to compensate for timing variations. This feedback loop enables the system to maintain adequate timing margins even at high clock frequencies by dynamically adjusting for measured delays.
3Use of energy by moving object
If gate overdrive is decreased to improve energy efficiency, then use of energy is improved, but delay mismatch increases
Solution Approach 1:
The patent changes the parameter of gate overdrive to lower values for energy efficiency, while compensating for the resulting increased delay mismatch through timing calibration. The system measures actual delays using transition patterns and applies trim values from a lookup table to compensate for the mismatch caused by reduced gate overdrive, thus maintaining performance while improving energy efficiency.
4Reliability
If timing calibration is applied to reduce wire delay mismatch, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the timing calibration process into distinct functional blocks: transition pattern generation, pattern transmission through the interconnect, delay measurement at the receiver, trim value calculation, and lookup table storage. This segmentation of the calibration function into modular components reduces overall device complexity by making each block independent and manageable, while still achieving improved reliability through comprehensive delay calibration.
Data Source
AI summary
One embodiment sets forth a timing calibration technique for on-chip source-synchronous, complementary metal-oxide-semiconductor (CMOS) repeater-based interconnect. Two transition patterns may be applied to calibrate the delay of an on-chip data or clock wire. Calibration logic is configured to apply the transition patterns and then trim the delays of the clock and data wires based on captured calibration patterns. The trimming adjusts the delay of the clock and data wires using a configurable delay circuit. Timing errors may be caused by crosstalk, power-supply-induced jitter (PSIJ), or wire delay variation due to transistor and wire metallization mismatch. Chip yields may be improved by reducing the occurrence of timing errors due to mismatched delays between different wires of an on-chip interconnect.