Semiconductor Interconnect Structure With Top Vias for Stable RC
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Solution Overview
Problem
The formation of interconnect structures in semiconductor devices faces challenges in achieving optimal resistance and capacitance (RC) characteristics, particularly due to the complexity of forming metal lines and vias with varying widths and heights, which affects connection performance and makes estimation difficult.
Innovation Solution
The implementation of a semiconductor device interconnect structure featuring metal lines and top vias formed through different deposition processes, where the metal lines and top vias have the same material composition but different structural characteristics, such as columnar and amorphous or polycrystalline structures, respectively, without an intervening layer, allowing for equal heights of wide and narrow metal lines with respective top vias, thereby improving connection performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal lines and vias are formed through the same process with same material composition, then manufacturing simplicity is maintained, but RC characteristics cannot be optimized for different line widths
Solution Approach 1:
The patent applies local quality by forming metal lines and top vias with different material compositions and structures at different locations. Specifically, metal lines are formed with a first material composition optimized for conductive pathways, while top vias are formed with a second material composition optimized for vertical connections. This localized differentiation allows each structure to have optimized RC characteristics for its specific function and geometry.
Solution Approach 2:
The patent segments the interconnect formation into distinct processes: metal line formation through a first deposition process, and top via formation through a second deposition process. This segmentation allows independent optimization of each structure's material composition and structural characteristics, enabling tailored RC performance for different interconnect elements rather than using a uniform formation approach.
2Reliability
If top vias are formed on metal lines with varying widths, then connection performance can be optimized, but estimation of interconnect performance becomes difficult
Solution Approach 1:
The patent changes material composition parameters to improve connection performance. By forming top vias with a different material composition than metal lines, the patent optimizes the electrical and mechanical properties of the via-metal line interface, enhancing connection reliability. This material parameter change allows for better adhesion and electrical performance in the via-to-metal-line connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the connection performance of semiconductor devices by ensuring consistent RC characteristics and simplifies the estimation of interconnect structure performance, while maintaining the benefits of the top via scheme regardless of width differences between wide and narrow metal lines.
Implementation Method 1
The 1st deposition process may be one of physical vapor deposition (PVD)
Implementation Method 2
the 2nd deposition process may be the other of the PVD and the CVD
Data Source
AI summary
A semiconductor device includes: a frontside structure including at least one of a front-end-of-line (FEOL) structure, a middle-of-line (MOL) structure, and a back-end-of-line (BEOL) structure; a 1st metal line on the frontside structure; and a 2nd metal line on the frontside structure, wherein the 1st metal line has a greater width than the 2nd metal line in a same direction, and the 1st metal line and the 2nd metal line have an equal height.