Interconnect Physical Layer Training for Bandwidth and Power Balance
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Solution Overview
Problem
Current interconnect architectures in computing systems face challenges in meeting the increasing demand for high-performance communication between multiple processors and devices, particularly in servers and mobile ecosystems, where they often compromise between performance and power efficiency.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that includes a layered protocol stack with a transaction layer, link layer, and physical layer, supporting point-to-point serial links and virtual channels, enabling efficient data transfer and power management while maintaining high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional multi-drop buses are used for interconnect, then device complexity is reduced, but communication performance and bandwidth are insufficient for modern multi-processor systems
Solution Approach 1:
The interconnect architecture is segmented into multiple independent point-to-point links rather than a shared bus. Each link connects specific processors or devices directly, enabling parallel communication paths. This segmentation increases bandwidth and reduces contention while managing complexity through modular link design and virtual channel multiplexing.
2Speed
If interconnect bandwidth is increased to support higher processing power, then communication speed improves, but power consumption increases
Solution Approach 1:
The interconnect supports dynamic link width adjustment where links can operate at different widths (e.g., 128-bit, 64-bit) depending on bandwidth requirements. The system can dynamically switch between full-width high-speed communication and narrower lower-power modes, allowing optimization of the speed-power tradeoff based on actual communication needs rather than maintaining constant high performance.
Solution Approach 2:
The architecture changes operational parameters such as link width and communication mode based on demand. By varying these parameters dynamically, the system achieves high bandwidth when needed while reducing power consumption during lower-demand periods, resolving the contradiction between speed and energy usage.
3Adaptability or versatility
If point-to-point serial links with virtual channels are implemented, then communication performance and scalability improve, but device complexity increases
Solution Approach 1:
The patent introduces virtual channels as an additional dimension of multiplexing within point-to-point links. Instead of requiring separate physical links for different communication types, the system creates multiple virtual channels (e.g., control, data, acknowledgment) that share the same physical medium. This dimensional approach increases scalability and adaptability while managing complexity through software-defined channel management.
4Productivity
If multiple sockets are used to increase processing power, then computing capability improves, but interconnect communication burden increases
Solution Approach 1:
The interconnect is segmented into dedicated point-to-point links for each socket rather than sharing a common bus. Each socket has dedicated communication paths to other sockets and devices, reducing communication contention and complexity per link while supporting multiple processors. This segmentation enables independent optimization of each link and simplifies error handling and routing.
Data Source
AI summary
A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.