Interconnect-Layer Transistor Structure for Charge Trapping Control
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Solution Overview
Problem
Transistors formed in the interconnect layer of semiconductor devices using high-k dielectric materials face issues such as charge trapping, leading to slower switching times and increased hysteresis due to oxygen vacancies and current leakage paths in the oxide-semiconductor channel.
Innovation Solution
Incorporating a bottom and top high-k terminal layers between the gate dielectric layer and the gate electrode, and between the gate dielectric layer and the oxide-semiconductor channel layer, respectively, to promote oxygen-to-metal bonding, thereby reducing charge trapping and current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high-k dielectric materials are used in the gate dielectric layer, then gate control and switching efficiency are improved, but charge trapping occurs leading to slower switching times and increased hysteresis
Solution Approach 1:
A terminal layer comprising hafnium oxide is introduced as an intermediary between the high-k dielectric material (e.g., aluminum oxide) and the oxide-semiconductor channel layer. This terminal layer mediates the interaction between the gate electrode structure and the channel, reducing charge trapping effects while preserving the high gate control efficiency provided by the high-k dielectric material. The terminal layer acts as a buffer that prevents direct charge trapping at critical interfaces.
Solution Approach 2:
The gate dielectric structure is formed as a composite material system combining multiple layers: a high-k dielectric material layer (such as aluminum oxide with dielectric constant greater than 20) and a terminal layer (hafnium oxide). This composite structure leverages the high dielectric constant of the first material for strong gate control while the terminal layer material provides improved electrical characteristics by reducing charge trapping, achieving both high power efficiency and reliability.
2Power
If high-k dielectric materials are used in the gate dielectric layer, then gate control is improved, but current leakage paths increase due to oxygen vacancies
Solution Approach 1:
The terminal layer serves as an intermediary that prevents the formation of current leakage paths between the gate electrode structure and the oxide-semiconductor channel layer. By positioning this layer at the interface, it blocks the propagation of harmful effects such as oxygen vacancy-induced leakage while allowing the high-k dielectric material to maintain its superior gate control capabilities.
3Ease of manufacture
If oxide-semiconductor channel layer is used, then integration with dielectric materials is improved, but oxygen vacancies create charge trapping and hysteresis
Solution Approach 1:
The terminal layer acts as a protective intermediary between the oxide-semiconductor channel layer and the gate dielectric structure, preventing oxygen vacancies in the channel layer from creating charge trapping sites. This maintains the manufacturing advantages of oxide-semiconductor integration while eliminating the associated reliability issues of hysteresis and charge trapping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances switching speed and reduces current leakage in transistors by minimizing charge trapping at the interface, resulting in improved performance and reliability.
Implementation Method 1
The bottom high-k terminal layer includes one or more materials that promote oxygen-to-metal bonding between the gate dielectric layer and the gate electrode
Implementation Method 2
forming a high-k gate dielectric layer of a backend transistor structure, where the high-k gate dielectric layer includes a first high-k dielectric material
Data Source
AI summary
A transistor structure may be formed in an interconnect layer of a semiconductor device. The transistor structure is formed such that a bottom high dielectric constant (high-k) terminal layer is included between a gate dielectric layer and an oxide-semiconductor channel layer of the transistor structure, and/or such that a top high-k terminal layer is included between the gate dielectric layer and a gate electrode of the transistor structure. The bottom high-k terminal layer may reduce the likelihood and/or magnitude of charge trapping that might otherwise occur at the interface between the gate dielectric layer and the gate electrode. The top high-k terminal layer may passivate loose bonds in the oxide-semiconductor channel layer, thereby reducing the likelihood and/or magnitude of charge trapping that might otherwise occur in the oxide-semiconductor channel layer.