Interconnect Via Barrier Structure for Lower Contact Resistance
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate, leading to challenges in achieving excellent performance while maintaining high integration, particularly in terms of electrical characteristics.
Innovation Solution
The semiconductor device includes a substrate with transistors, interlayer insulating layers, lower and upper interconnection lines, and an etch stop layer, where the upper interconnection line features a via portion with a barrier pattern and conductive pattern, utilizing barrier layers with varying nitrogen concentrations and thicknesses to reduce contact resistance and improve electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFETs are scaled down to maintain high integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The barrier pattern is designed with non-uniform nitrogen concentration distribution, where the first barrier layer has higher nitrogen concentration near the lower interconnection line interface and the second barrier layer has lower nitrogen concentration toward the upper interface. This local variation in material composition optimizes electrical characteristics at different locations within the via structure, reducing contact resistance while maintaining scalability.
2Reliability
If the barrier layer has high nitrogen concentration, then diffusion barrier performance improves, but electrical resistivity increases
Solution Approach 1:
The invention employs a gradient nitrogen concentration profile within the barrier pattern by stacking two barrier layers with different nitrogen concentrations. The first barrier layer (higher nitrogen concentration) provides superior diffusion barrier performance at the critical interface with the lower interconnection line, while the second barrier layer (lower nitrogen concentration) reduces overall electrical resistivity of the via structure, achieving an optimal balance between barrier performance and electrical conductivity.
Data Source
AI summary
Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.