Semiconductor Interconnect Via Structure With Enlarged Bottom Opening
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Solution Overview
Problem
As feature sizes in semiconductor manufacturing continue to shrink, there is a need for structures and methods that can effectively reduce parasitic capacitance and increase conduction speed between metal interconnects, while also addressing challenges in forming vias due to high aspect ratios.
Innovation Solution
An interconnect structure is formed using an anisotropic plasma etching process to create openings in a second dielectric layer, exposing a conductive feature in a first dielectric layer. A plasma process converts the upper portion of the conductive feature into a material that is later removed by a multi-step wet cleaning process, enlarging the bottom portion of the opening. This enlarged opening is then filled with a conductive material to form a via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are shrunk to increase integration density, then integration density is improved, but parasitic capacitance between metal interconnects increases
Solution Approach 1:
The patent applies local quality by using low-k dielectric material specifically in the regions between metal interconnects to reduce parasitic capacitance, while maintaining the shrunk feature sizes for high integration density. The low-k dielectric is selectively placed where capacitance reduction is needed without affecting the overall device architecture.
2Object-generated harmful factors
If low-k dielectric materials are used to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by performing plasma treatment on the low-k dielectric material before metal interconnect formation. This pre-treatment modifies the dielectric surface properties in advance, ensuring better metal adhesion and reducing subsequent manufacturing steps' complexity. The plasma treatment is done during the dielectric layer formation process rather than as a separate post-processing step.
3Ease of manufacture
If conventional etching processes are used to form vias, then manufacturing simplicity is maintained, but via aspect ratios become too high for reliable filling
Solution Approach 1:
The patent applies parameter changes by modifying the etching process parameters, specifically using a multi-step etching process with different selectivity ratios. The first etching step uses a mask with selectivity of 1:1 to the mandrel, and the second step uses a different etch chemistry to achieve the desired via profile. This changes the etching parameters to control the via aspect ratio while maintaining manufacturing feasibility.
4Manufacturing precision
If CMP slurry etching is used during planarization, then planarization is achieved, but the upper surface of conductive features recesses
Solution Approach 1:
The patent applies preliminary anti-action by performing plasma treatment on the conductive features before the CMP process. This pre-treatment creates a protective layer or modifies the surface properties of the conductive features, preventing excessive etching by the CMP slurry. The plasma treatment counteracts the harmful etching effect before it occurs during planarization, maintaining the conductive feature height and ensuring reliable electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces recessing of the upper surface of the conductive feature and improves the reliability of electrical connections by forming vias with enlarged bottom portions, which catch CMP slurry and reduce etching effects, thereby enhancing conduction speed and reducing RC delay.
Implementation Method 1
an anisotropic plasma etching process is performed to form an opening in a second dielectric layer
Implementation Method 2
the conductive feature is treated with a plasma process, wherein the plasma process converts an upper portion of the conductive feature into a first material
Implementation Method 3
a multi-step wet cleaning process is performed using deionized water (DIW) to clean the opening. The DIW dissolves and remove the first material, thereby enlarging a bottom portion of the opening
Implementation Method 4
The enlarged bottom portion of the via formed may catch CMP slurry seeping down through cracks between the via and the second dielectric layer, and may reduce recessing of the upper surface of the conductive feature due to etching of the conductive feature by the slurry
Data Source
AI summary
A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.