Multi-Level Interconnect Structure with Vertical Via Bypass
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Solution Overview
Problem
Modern semiconductor integrated circuits face increased resistance and reduced power efficiency due to the dense, multi-level interconnect structures, which are challenging to address with conventional fabrication methods.
Innovation Solution
The method involves forming a multi-level interconnect structure by splitting a conventional interconnection level into two sub-levels, allowing for relaxed line pitches and maintaining routing density through direct vertical vias that bypass sub-levels, reducing the need for complex multi-patterning techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dense line patterns are used in multi-level interconnect structures, then routing density is improved, but line resistance increases
Solution Approach 1:
The patent introduces an intermediate sub-level between the first and second interconnection levels, creating a three-tier structure. This dimensional expansion allows signal routing to occur at multiple vertical levels, reducing the horizontal density requirement at each individual level while maintaining overall routing capacity. The intermediate sub-level provides additional routing space that reduces line resistance without sacrificing total routing density.
Solution Approach 2:
The patent divides the conventional single interconnection level into multiple sub-levels (first sub-level and second sub-level), with each sub-level containing a subset of the original lines. This segmentation distributes the routing load across multiple layers, reducing the density and resistance of individual lines while maintaining the overall interconnect functionality.
2Ease of manufacture
If conventional single interconnection levels are used, then manufacturing process is simple, but routing density is reduced
Solution Approach 1:
The patent adds a vertical dimension by introducing an intermediate sub-level between existing interconnection levels. This approach maintains compatibility with conventional planar manufacturing processes while utilizing the third dimension to increase routing density without requiring complex multi-patterning techniques.
Solution Approach 2:
The patent forms the intermediate sub-level with relaxed pitch requirements before completing the full interconnect structure. This preliminary action allows standard lithographic processes to be used, avoiding the need for complex multi-patterning that would be required if all levels were formed simultaneously at high density.
3Quantity of substance
If pitch is reduced to increase routing density, then more lines fit in a given area, but time-dependent dielectric breakdown performance deteriorates
Solution Approach 1:
By distributing lines across multiple vertical levels including an intermediate sub-level, the patent reduces the horizontal pitch requirement at each level. This dimensional distribution maintains adequate spacing between adjacent lines, preserving dielectric breakdown performance while achieving high overall routing density through vertical stacking.
Solution Approach 2:
The patent segments the line set into multiple sub-levels, reducing the number of lines per level and thereby increasing the effective pitch at each level. This segmentation maintains sufficient dielectric spacing to prevent breakdown while achieving high total routing capacity across all levels.
Data Source
Figure 1A~1B
Figure 2A~2C
Figure 3A~3C
AI summary
According to an aspect of the present inventive concept there is provided a method for forming a multi-level interconnect structure for a semiconductor device, the method comprising: forming a first interconnection level including a set of conductive lines arranged in a first common horizontal plane of the first interconnection level and extending parallel to a first direction, forming a second interconnection level, wherein forming the second interconnection level comprises: forming, on the first interconnection level, a first sub-level of the second interconnection level, the first sub-level including a set of conductive lines arranged in a first common horizontal plane of the second interconnection level and extending parallel to a second direction transverse to the first direction, and forming, on the first sub-level of the second interconnection level, a second sub-level of the second interconnection level, the second sub-level including a set of conductive lines arranged in a second common horizontal plane of the second interconnection level and extending parallel to the second direction, wherein the first and the second sub-levels of the second interconnection level are formed as consecutive sub-levels and wherein said set of lines of the first sub-level of the second interconnection level and said set of lines of the second sub-level of the second interconnection level are horizontally displaced in relation to each other, and forming a vertical via for interconnecting a line of said set of lines of the first interconnection level and a line of said set of lines of the second sub-level of the second interconnection level, wherein the via extends past said set of lines of the first sub-level of the second interconnection level in a space between a pair of adjacent lines of said set of lines of the first sub-level of the second interconnection level.