Metallic Interconnect Layout for Via Group Coverage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device manufacturing processes result in silica residue etching abnormalities and reduced production yield due to steps created by underlying interconnects during the formation of via holes, leading to contamination from flaking insulating materials.
Innovation Solution
The first layer metallic interconnect is strategically positioned to cover the entire via group, preventing abnormal etching of silica residue and ensuring a flat surface by overlapping with all vias, thereby maintaining the integrity of the interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a silica coating process is used to planarize the interlayer insulating film, then the surface flatness is improved, but silica residue remains in the steps created by underlying interconnects, leading to abnormal etching and contamination
Solution Approach 1:
The underlying interconnect is designed to extend in advance to cover the via group region before the silica coating and etching processes occur. This preliminary geometric configuration prevents step formation at the via locations, thereby preventing silica residue accumulation and subsequent abnormal etching during the via hole formation process
Solution Approach 2:
The extended interconnect structure acts as a preventive measure that counteracts the harmful effect of step formation. By having the interconnect cover the via group area beforehand, the design preemptively eliminates the condition that would lead to silica residue entrapment and abnormal etching
2Device complexity
If the underlying interconnect does not cover the via group, then the interconnect pattern is simpler, but steps are created that trap silica residue and cause production yield reduction
Solution Approach 1:
The interconnect pattern is designed in advance to extend beyond the standard interconnect path and cover the via group region. This preliminary geometric extension, while slightly increasing pattern complexity, prevents silica residue entrapment and ensures high production yield by eliminating the root cause of manufacturing defects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances production yield by preventing silica residue etching abnormalities and maintaining a flat surface, ensuring reliable electrical coupling between interconnect layers.
Implementation Method 1
a typical technology is to achieve a planarization of an interlayer insulating film by employing a silica film produced via a rotation coating process
Implementation Method 2
an interlayer insulating film such as a plasma oxidization film is deposited
Implementation Method 3
a wet etch process is conducted, and subsequently, a dry etch process is conducted to form via holes
Implementation Method 4
a wet etch process is conducted, and subsequently, a dry etch process is conducted to form via holes
Data Source
AI summary
A silica residue is generated, due to a presence of a step formed by a presence of the first layer metallic interconnect, and then, the residual silica is etched to form hollow portions when vias for the metallic interconnect provided in a layer above thereof is formed, and further, insulating materials remained above the hollow portions flakes off to create contaminants, leading to a reduction in the production yield. In the present invention, interconnects provided in a layer underlying a via group, which are provided for coupling to the upper layer interconnect layer, are disposed so as to cover vias composing its via group.