Interconnect Via Etch Profile Control for Vertical Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving vertical etch profiles for vias in interconnect structures, leading to potential leakage and contact between vias and metal lines, which affects the performance of integrated circuits.
Innovation Solution
The method involves forming an etch stop layer, a metal oxide layer, and an interlayer dielectric layer, followed by the deposition of a capping layer and specific etching processes to achieve substantially vertical via profiles, preventing over-etching and ensuring precise dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for via formation, then the manufacturing process is simple, but the etch profile becomes non-vertical leading to leakage and contact between vias and metal lines
Solution Approach 1:
The etching process is divided into multiple sequential steps: forming a mandrel structure, depositing first and second spacers, performing first and second etching operations. Each step creates a portion of the final via structure, allowing precise control over the etch profile at different stages rather than attempting to achieve the complete profile in a single step.
Solution Approach 2:
The mandrel structure and spacer layers are formed in advance before the actual via etching. These preliminary structures serve as templates and protective elements that guide the etching process to achieve the desired vertical profile. The first spacer is deposited and patterned before the second etching operation, preparing the structure for subsequent processing steps.
2Length of moving object
If aggressive etching is used to reach deep vias, then via depth is achieved, but over-etching occurs causing leakage and contact with metal lines
Solution Approach 1:
The second spacer acts as an intermediary protective layer during the second etching operation. It is deposited conformally over the first spacer and mandrel, then selectively removed to define the via opening. This intermediary structure prevents the etch from progressing too far, serving as a built-in stop mechanism that protects against over-etching and maintains via isolation from metal lines.
Solution Approach 2:
The process uses the previously formed structures (mandrel, first spacer, second spacer) as feedback references for the etching depth. Each etching step is controlled by the physical presence and dimensions of these underlying structures, allowing the process to self-regulate and prevent over-etching without requiring complex real-time monitoring systems.
3Area of moving object
If via dimensions are reduced for higher density, then storage capacity increases, but etch profile control becomes more difficult
Solution Approach 1:
The spacer structures provide locally different properties at different radial positions from the via center. The first and second spacers create zones with different protective characteristics during etching, allowing the process to maintain vertical profiles even at reduced via dimensions. This local differentiation of protective qualities enables precise control over the etch front as it progresses through the material.
Data Source
AI summary
A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.