Interconnect Via Etching With Etch Stop Layers to Prevent Arcing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing number of circuit elements in modern integrated circuits requires a corresponding increase in electrical connections, which poses challenges in forming efficient and reliable vias between stacked metallization layers due to high aspect ratios and potential arcing events during plasma etching.
Innovation Solution
The formation of insulating films between interconnect structures to reduce potential differences and prevent arcing, combined with selective etching processes to form vias, ensuring precise and reliable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of circuit elements is increased to meet advanced circuit requirements, then the circuit functionality is improved, but the number of electrical connections increases leading to more complex metallization layers and higher aspect ratios in via formation
Solution Approach 1:
The patent divides the via formation process into multiple etching stages with different etch selectivities. First, a mandrel is formed and a first etch process creates an initial cavity. Then the mandrel is removed and a second etch process completes the via formation. This segmentation allows control over the high aspect ratio via structure while managing the complexity of connecting numerous circuit elements.
2Productivity
If plasma etching is used to form vias through thick dielectric layers, then the via formation efficiency is improved, but arcing events occur causing contamination and yield loss
Solution Approach 1:
The patent introduces an intermediary etch stop layer between the dielectric layer and the underlying structure. This etch stop layer acts as a mediator that prevents direct plasma contact with the underlying metal or substrate, thereby preventing arcing events while still allowing efficient via formation through the thick dielectric layer using plasma etching.
Solution Approach 2:
The patent performs preliminary actions by forming the etch stop layer and mandrel structure before the main via etching process. The mandrel is formed first to define the via location and provide structural support during etching. The etch stop layer is deposited beforehand to prevent arcing during the subsequent plasma etching process, ensuring reliable via formation without contamination.
3Reliability
If via aspect ratios are reduced to prevent arcing, then the reliability of via formation is improved, but the via depth is reduced compromising electrical connection effectiveness
Solution Approach 1:
The patent changes the parameter of etch selectivity by using different etch processes with different selectivities for different layers. The first etch process has high selectivity for the dielectric layer relative to the etch stop layer, allowing deep etching without affecting the underlying structure. The second etch process completes the via with controlled depth. This parameter change allows maintaining high via aspect ratios while preventing arcing through the etch stop layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the likelihood of arcing events, minimizing contamination and yield loss, and enhances the reliability and efficiency of electrical connections in integrated circuits.
Implementation Method 1
plasma etching
Data Source
AI summary
An integrated circuit device and a method of manufacturing the same are provided. The method includes steps of: forming a semiconductor device on a substrate; forming a first interconnect structure and a dielectric layer over the semiconductor device; and forming a second interconnect structure over the first interconnect structure, wherein the formation of the second interconnect structure includes: forming an insulating film over the first interconnect structure; depositing an etch stop layer over the insulating film, wherein the etch stop layer and the insulating film include different materials; depositing an isolation layer over the etch stop layer; performing a first etching operation to form a via penetrating the isolation layer and exposing the etch stop layer; and performing a second etching operation to extend the via downward to penetrate the etch stop layer and the insulating film and expose a portion of the first interconnect structure.