Semiconductor Interconnect Via Geometry for Higher Line Density
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Solution Overview
Problem
The challenge in miniaturizing integrated circuits is the efficient electrical connection between conductive traces and vias, as existing photolithographic processes struggle to create precise and dense interconnect structures.
Innovation Solution
A method is developed to form a conductive via by removing a portion of a conductive member exposed by a second conductive line, where the second conductive line is formed prior to the via, allowing for a non-orthogonal cross-section that increases the density of conductive lines by adjusting the cross-sectional angles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic processes are used to form conductive traces and vias, then manufacturing simplicity is maintained, but manufacturing precision and integration density are insufficient
Solution Approach 1:
The conductive line is formed in advance before the via is created. The method forms a first conductive line, then forms a via that exposes a portion of the first conductive line, and finally forms a second conductive line over the via. This preliminary formation of the first conductive line enables precise via placement and subsequent second conductive line formation, achieving high manufacturing precision through staged processing.
Solution Approach 2:
The conductive interconnect structure is divided into multiple segments: a first conductive line, a via, and a second conductive line. This segmentation allows each component to be formed with optimized processes and parameters, improving overall manufacturing precision while managing process complexity through modular fabrication steps.
2Productivity
If orthogonal cross-sections are used for conductive lines, then manufacturing simplicity is maintained, but integration density is limited
Solution Approach 1:
The patent employs non-orthogonal cross-sectional geometries for conductive lines, specifically using angled sides rather than purely vertical or horizontal orientations. This asymmetric design allows conductive lines to be packed more densely while maintaining electrical performance, thereby increasing integration density without requiring complex multi-dimensional routing.
Solution Approach 2:
The invention transitions from traditional orthogonal (two-dimensional grid-like) conductive line arrangements to non-orthogonal configurations that utilize angular orientations. This dimensional change in the cross-sectional geometry enables more efficient space utilization and higher line density within the same planar area, boosting productivity in terms of integration density.
Data Source
AI summary
A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.