Interconnect Via Profile Control for Void-Free Semiconductor Routing
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into smaller areas, challenges arise in maintaining efficient interconnects and reducing feature sizes, particularly in forming trench and via openings with precise profiles to prevent voids and improve yield.
Innovation Solution
A method involving the formation of a dielectric layer with specific precursors, an anti-reflective layer, and a hardmask, followed by a single etching process to create trench and via openings with controlled profiles, and subsequent removal of etch stop layers to achieve vertical sidewalls and reduce pitch, allowing for more efficient conductive material filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multi-step etching processes are used to form trench and via openings, then the process is simpler to implement, but the sidewall profile control is poor leading to voids and reduced yield
Solution Approach 1:
The patent combines multiple etching operations into a single etching process that simultaneously forms both trench openings and via openings. This unified approach uses a shared etch stop layer and synchronized etching conditions to achieve precise sidewall profile control for both feature types, eliminating the profile control issues that arise from separate processing steps while reducing overall process complexity
Solution Approach 2:
The patent introduces a shared etch stop layer that serves as an intermediary reference plane for both trench and via etching operations. This etch stop layer is positioned at a common depth and provides a uniform stopping point during the single etching process, enabling consistent sidewall angles and preventing void formation by ensuring precise depth control for both feature types simultaneously
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but the difficulty of forming precise trench and via profiles increases
Solution Approach 1:
By merging the etching processes for trenches and vias into a single operation with shared process parameters, the patent achieves consistent profile control even at reduced feature sizes. The unified process ensures that both trench and via sidewalls are formed under identical conditions, maintaining precision as feature dimensions are scaled down to increase integration density
Solution Approach 2:
The patent optimizes etching parameters such as gas flow rates, power levels, and pressure conditions to achieve the desired sidewall profiles at smaller feature sizes. By carefully adjusting these parameters in the single etching process, the method maintains manufacturing precision despite the reduced dimensions required for higher integration density
3Manufacturing precision
If separate etching processes are used for trenches and vias, then each can be optimized independently, but the process time and complexity increase
Solution Approach 1:
The patent merges the trench etching and via etching into a single simultaneous process operation. By using a shared etch stop layer and coordinated masking strategy, both feature types are etched in one go, reducing the total process time while maintaining profile control through unified process parameters and a common reference plane
Solution Approach 2:
The patent performs preliminary preparation of the etch stop layer and masking structure before the single etching operation. The etch stop layer is pre-formed at the target depth, and the mask is patterned to define both trench and via locations simultaneously, enabling the subsequent single etching process to proceed efficiently without requiring intermediate steps or re-alignment operations
Data Source
AI summary
A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.