Semiconductor Interconnect via Recess Elimination
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Solution Overview
Problem
Conventional copper interconnect formation methods in semiconductor devices face misalignment issues during the photolithography process, leading to via recesses and unstable yield due to mask misalignment, which affects the accuracy and reliability of the interconnects.
Innovation Solution
A method involving the formation of a dielectric layer, patterning, and filling with a copper alloy layer, followed by planarization and conversion of the top surface into a metal oxide layer, with subsequent etching and radiation exposure to create recess-free interconnect features that stop at the metal oxide layer, avoiding undercutting and ensuring accurate alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography with mask alignment is used to form copper interconnects, then the interconnect structure can be formed, but misalignment occurs leading to via recesses and unstable yield
Solution Approach 1:
The patent introduces a sacrificial oxide layer as an intermediary between the copper interconnect and the dielectric layer. This oxide layer serves as a buffer that absorbs misalignment errors during etching, preventing direct contact between misaligned features and eliminating via recesses. The oxide mediator allows the etch to self-correct alignment deviations without creating harmful recesses at the copper-dielectric interface.
Solution Approach 2:
The patent performs preliminary oxidation of the copper layer before the final etching step. By converting the copper surface to an oxide layer in advance, the process creates a sacrificial buffer that will be selectively removed later. This preliminary action prepares the structure to absorb potential misalignment issues before the critical interconnect formation step, preventing via recesses from forming in the first place.
2Productivity
If photoresist misalignment is allowed to occur during photolithography, then the process is simpler and faster, but via recesses are formed causing unstable yield
Solution Approach 1:
The patent converts the harmful effect of photoresist misalignment into a beneficial outcome by introducing the sacrificial oxide layer. Instead of preventing misalignment entirely (which would require slower, more precise processes), the oxide layer absorbs the misalignment error and transforms it into a non-critical defect that does not create via recesses. The misalignment that would normally be harmful is now tolerated and even utilized as a built-in alignment buffer.
3Device complexity
If conventional copper etching is performed without a sacrificial oxide layer, then the process is simpler, but undercutting occurs and via recesses are formed
Solution Approach 1:
The sacrificial oxide layer acts as an intermediary protective layer during the etching process. It sits between the etchant and the copper-dielectric interface, preventing direct etching that would cause undercutting and via recesses. The oxide mediator is selectively removed after serving its protective function, leaving clean, precise interconnect features without the harmful geometric defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy and reliability of interconnect formation by eliminating via recesses and ensuring precise alignment, resulting in improved yield and stability of semiconductor interconnects.
Implementation Method 1
converting a top surface into a metal oxide layer
Implementation Method 2
A radiation exposure process is thereafter performed on the metal oxide layer to convert it into a non-oxidized metal layer
Data Source
AI summary
A method for forming a semiconductor interconnect structure includes forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. A metal layer fills the opening and covers the dielectric layer. The metal layer is planarized so that it is co-planar with a top of the dielectric layer. A treating process is performed on the metal layer to convert a top surface thereof into a metal oxide layer. A copper-containing layer is then formed over the metal oxide layer and the dielectric layer. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the metal oxide layer and does not etch into the underlying metal layer. A radiation exposure process is thereafter performed on the metal oxide layer to convert it into a non-oxidized metal layer.