Semiconductor Interconnect Via Undercut for Lower RC Delay
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Solution Overview
Problem
As semiconductor feature sizes shrink, forming vias with high aspect ratios becomes challenging due to parasitic capacitance and RC delay issues, which are exacerbated by the shrinking dimensions and the need for low-k dielectric materials in advanced semiconductor manufacturing processes.
Innovation Solution
An interconnect structure is formed using an anisotropic plasma etching process followed by a hydrogen and argon plasma treatment to convert the upper portions of conductive features into materials that can be dissolved by deionized water, thereby enlarging the via openings and reducing parasitic capacitance by creating undercuts in the IMD layer, allowing for better filling and reduced CMP slurry seepage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are shrunk to increase integration density, then integration density is improved, but parasitic capacitance and RC delay increase
Solution Approach 1:
The patent employs low-k dielectric materials with porous structures to reduce parasitic capacitance between interconnects. The porous nature of these materials provides lower dielectric constants, directly addressing the harmful capacitance effect that increases with higher integration density.
Solution Approach 2:
The patent applies different dielectric materials with varying k-values in different regions of the interconnect structure. Low-k dielectric materials are specifically placed in critical areas where parasitic capacitance has the most impact, while maintaining other structural requirements in different zones.
2Object-generated harmful factors
If low-k dielectric materials are used to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the dielectric structure into multiple segments with different k-values, placing low-k materials only in specific regions where parasitic capacitance reduction is most critical. This segmentation allows selective application of complex materials and processes only where needed, rather than throughout the entire structure.
Solution Approach 2:
The patent modifies physical and chemical parameters of the dielectric materials, such as porosity and composition, to achieve lower k-values. These parameter changes enable capacitance reduction while managing manufacturing complexity through controlled material properties rather than entirely new process steps.
3Object-generated harmful factors
If via openings are enlarged to reduce parasitic capacitance, then parasitic capacitance is reduced, but via filling difficulty increases
Solution Approach 1:
The patent performs preliminary plasma treatment and surface preparation on the via walls before filling. This preliminary action modifies the surface properties to enhance adhesion and enable more effective filling processes, even for enlarged via openings where capacitance reduction is prioritized.
Solution Approach 2:
The patent employs composite material structures in the via regions, combining different materials with complementary properties. The composite structure allows for both enlarged opening dimensions (reducing capacitance) and improved fillability through material combinations that address adhesion and filling challenges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively enlarges via openings, reducing CMP slurry seepage and electrical resistance, enhancing the reliability of the interconnects and reducing RC delay in semiconductor devices.
Implementation Method 1
an anisotropic plasma etching process is performed to form an opening in a second dielectric layer
Implementation Method 2
the conductive feature is treated with a plasma process, wherein the plasma process converts an upper portion of the conductive feature into a first material
Implementation Method 3
The DIW dissolves and remove the first material, thereby enlarging a bottom portion of the opening
Implementation Method 4
a planarization process to remove excess conductive material
Data Source
AI summary
A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.