Semiconductor Interconnect Structure With Wide Pad for NanoTSV Alignment
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Solution Overview
Problem
The integration of power delivery networks in semiconductor components faces challenges due to increased device density, including via diameters larger than buried power rails, shorting issues, and overlay errors between back-side processed nTSVs and front-side processed BPRs, which are exacerbated by thinning and bonding processes.
Innovation Solution
A method to produce a nano-sized interconnect structure by forming a trench, etching a cavity at its foot, and filling it with conductive material to create a wide contact pad, followed by processing a nanoTSV connection from the back side to connect the front and back sides of the semiconductor substrate, ensuring a reliable contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If narrow Through Semiconductor Via connections (nTSVs) are produced from the back side to contact buried power rails, then the power delivery network can be integrated in the back end of line, but the via diameter becomes larger than the width of the buried rails causing shorting issues
Solution Approach 1:
A liner is deposited on the sidewalls and bottom of the via opening before etching, and is selectively removed only from the bottom. This preliminary action prepares the structure to accommodate the larger via diameter while preventing shorting, as the remaining sidewall liner provides insulation during subsequent processing steps.
Solution Approach 2:
The liner material acts as an intermediary between the via opening and the buried power rail. By selectively removing the liner from the bottom while retaining it on the sidewalls, the liner mediates the transition from an insulating state during etching to a controlled conductive state for power delivery, preventing shorting while enabling connectivity.
2Ease of manufacture
If thinning and bonding steps are performed to enable back side processing, then the power delivery network can be formed, but overlay errors occur between back-side processed nTSV and front-side processed BPR
Solution Approach 1:
The liner is deposited and selectively removed from the bottom of the via opening before metal filling. This preliminary preparation creates a robust structure that can tolerate overlay errors from thinning and bonding, as the liner provides a defined geometric reference that maintains alignment between the via and the buried power rail even when positional deviations occur.
3Reliability
If the liner is removed from the bottom of the via to enable connection to the buried rail, then electrical connectivity is achieved, but areas where the nTSV is shorted to the substrate occur due to larger via diameter
Solution Approach 1:
The liner is selectively removed from the bottom of the via opening before metal filling, while retaining it on the sidewalls. This preliminary selective removal enables electrical connectivity to the buried power rail by exposing the rail surface, while the remaining sidewall liner prevents shorting to the substrate by maintaining insulation on the via walls throughout the metal filling process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Resolves shorting and overlay-related problems by providing a large contact area for nanoTSVs, enhancing the reliability and precision of interconnects in high-density semiconductor components.
Implementation Method 1
etching the material of the intermediate layer from inside the trench to form a cavity at the foot of the trench
Data Source
AI summary
A method producing a nano-sized interconnect structure that electrically connects the front side of a semiconductor substrate to the back side of the substrate is provided. In one aspect, the method produces a semiconductor component such as an integrated circuit chip that includes active devices formed on the front side of the substrate, and an interconnect network such as a power delivery network on the back side of the substrate. The substrate includes a lower semiconductor layer, an intermediate layer, and an upper layer. A trench is formed through the upper layer, the material of the intermediate layer is etched from inside the trench to form a cavity at the foot of the trench, and the trench and the cavity are filled with an electrically conductive material to form a buried rail with a wide contact pad at the foot of the rail, that is, wider than the width of the rail and extending between the front and back surfaces of the intermediate layer. A nanoTSV connection is processed from the back of the substrate, the nanoTSV contacting the contact pad, to thereby form the interconnect structure.