Protection Liner on Interconnect Wire for Wider Via Processing Window
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) scale down, the increased spacing reductions between conductive features lead to higher capacitance, power consumption, and time delay, which existing manufacturing techniques struggle to address effectively.
Innovation Solution
The formation of a protection liner, such as graphene, on interconnect wires to prevent the misalignment and damage of interconnect vias, using materials that resist etching and maintain isolation structures, thereby enhancing the processing window for via formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between conductive features is reduced to increase density, then the element density increases, but the capacitance increases and power consumption increases
Solution Approach 1:
The patent introduces air spacer structures that segment the dielectric material between adjacent conductive features. By replacing a portion of the continuous dielectric material with air spacers, the capacitance between adjacent conductors is reduced, thereby lowering power consumption while maintaining high element density.
2Quantity of substance
If the spacing between conductive features is reduced to increase density, then the element density increases, but the time delay increases
Solution Approach 1:
The air spacer structures segment the dielectric pathways between conductive features, reducing the capacitance and thereby reducing the RC time delay. This allows signals to propagate faster between closely spaced elements, reducing time delay while maintaining high density.
3Manufacturing precision
If a protection liner is formed on interconnect wires to prevent via misalignment damage, then the processing window for via formation increases, but the device complexity increases
Solution Approach 1:
The protection liner is formed on the interconnect wires before the via formation process. This preliminary protective layer prevents damage to the wire tops during subsequent via etching and formation steps, enlarging the processing window and improving manufacturing precision without significantly increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The protection liner reduces electron scattering, maintains resistivity, and increases the reliability and efficiency of ICs by preventing damage to dielectric layers and air spacer structures during via formation, thus improving device performance.
Implementation Method 1
The protection liner reduces electron scattering, maintains resistivity
Data Source
AI summary
In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.