Interconnect Writeback Bypass for Coherency Control
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Solution Overview
Problem
In data processing systems with multiple masters connected via an interconnect, writebacks often occur out of order, leading to data corruption and increased power consumption due to the need to stall snoop requests and resend them, which can result in deadlock situations and performance issues.
Innovation Solution
The interconnect circuitry is configured to allow writeback transactions to proceed independently of coherency control circuitry, ensuring that writebacks complete without being held up by other transactions, thus maintaining data coherency and reducing delays and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If coherency control circuitry is used to maintain ordering of transaction requests, then data coherency is improved, but writeback transactions are delayed and power consumption increases
Solution Approach 1:
The patent segments transaction handling into two distinct paths: a coherency-controlled path for regular transactions and a dedicated bypass path for writeback transactions. This segmentation allows writebacks to proceed independently without being subjected to coherency control overhead, thereby reducing power consumption while maintaining data coherency for other operations.
Solution Approach 2:
The patent introduces a bypass mechanism as an intermediary pathway that allows writeback transactions to circumvent the coherency control circuitry. This intermediary path ensures that writebacks are not stalled by coherency protocols, reducing the need for resending transactions and thereby lowering power consumption.
2Reliability
If snoop requests are stalled to ensure writeback ordering, then data coherency is improved, but transaction latency increases and deadlock situations may arise
Solution Approach 1:
The patent separates writeback transaction handling from regular transaction handling by providing a dedicated bypass path. This segmentation eliminates the need to stall snoop requests for writeback ordering, as writebacks proceed independently through the bypass, thereby reducing transaction latency and preventing deadlock situations while maintaining data coherency.
Solution Approach 2:
The bypass path is预先 established to handle writeback transactions before they can interfere with other transactions. By providing this preliminary pathway, writebacks complete without causing stalls or deadlocks, reducing overall transaction latency.
3Reliability
If writebacks are controlled by coherency control circuitry, then transaction ordering is maintained, but system performance decreases due to stalling and resending
Solution Approach 1:
The patent divides the transaction processing system into two independent channels: a coherency-controlled channel for maintaining transaction ordering of regular operations, and a bypass channel for writeback transactions. This segmentation allows writebacks to proceed without stalling, improving system performance while the coherency channel maintains ordering for other transactions.
Solution Approach 2:
The bypass mechanism serves as an intermediary that handles writeback transactions separately from the main coherency control flow. This intermediary path prevents writebacks from causing stalls and resending, thereby improving system performance while the coherency control circuitry continues to maintain ordering for other transactions.
Data Source
AI summary
Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.