Interconnected Command Address Resources for Wafer Testing
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Solution Overview
Problem
Testing multiple memory dies on a wafer at once incurs high costs due to the need for probe cards with a high pin count, which increases the cost of testing at the wafer level compared to testing at the memory die level.
Innovation Solution
The implementation of a reduced pin count probe card that uses repeater logic circuits and control logic circuits to route test signals between CA pads on different memory dies, allowing for testing of multiple memory dies with a lower number of pins, thereby reducing overall testing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If probe cards with high pin count are used to test multiple memory dies on a wafer simultaneously, then testing capability is improved, but cost increases
Solution Approach 1:
The patent introduces CA pad interconnect structures as intermediary elements that couple CA pads from different memory dies together. These interconnects act as mediators that allow test signals to be shared across multiple dies through common CA pads, reducing the number of probe card pins needed while maintaining the ability to test multiple dies simultaneously
Solution Approach 2:
The patent implements universal CA pad structures where certain CA pads are designed to serve multiple memory dies simultaneously. These shared CA pads can receive and transmit test signals to multiple dies through the interconnect structures, allowing a single probe card pin to effectively test multiple dies, thereby reducing overall pin count requirements
2Productivity
If wafer-level testing is performed, then testing efficiency is improved, but probe card cost increases due to high pin count
Solution Approach 1:
The CA pad interconnect structures serve as intermediary components that enable signal sharing between multiple memory dies. By coupling CA pads from different dies through these interconnects, the system allows test signals to be distributed to multiple dies through fewer probe card pins, reducing device complexity while preserving wafer-level testing efficiency
Solution Approach 2:
The patent merges CA pad resources from multiple memory dies into shared test signal paths. By combining the CA pad functionality of multiple dies through interconnect structures, the system enables simultaneous testing of multiple dies using a reduced number of probe card pins, thereby reducing device complexity while maintaining high testing efficiency
Data Source
AI summary
Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.