Interconnected Memory Die Read-Write Sequencing to Reduce Timing Delays
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Solution Overview
Problem
Interconnected die architectures in memory devices experience timing delays during data transfer, impacting the overall performance of read and write operations.
Innovation Solution
Implementing an asymmetric read-write sequence that differs the order of data access between interface and linked dies, minimizing the impact of timing delays associated with the interconnected die architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is transferred between interconnected dies, then memory capacity and integration are improved, but timing delays increase
Solution Approach 1:
The patent applies preliminary action by performing write operations to the linked die before read operations are needed. The memory controller writes data to the linked die in advance, so that when read operations occur, the data is already available, eliminating timing delays and allowing the system to achieve peak bandwidth utilization without waiting for inter-die transfer completion.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting the sequencing of read and write operations based on the interconnected die architecture. The memory controller dynamically schedules write operations to the linked die ahead of read operations, adapting the operation sequence to minimize the impact of fixed inter-die transfer timing on overall performance.
2Loss of time
If asymmetric read-write sequence is implemented, then timing impact is reduced, but operation complexity increases
Solution Approach 1:
The patent applies self-service by having the memory controller automatically manage the asymmetric read-write sequencing without requiring external intervention or complex coordination. The controller independently determines and executes the optimal operation sequence based on the known architecture, simplifying the overall system while reducing timing impact.
Data Source
AI summary
Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.