Vertical Memory String Fabrication via Interconnected Openings

The patent transitions from traditional horizontal memory cell arrangement to vertical stacking architecture, where memory cells are arranged in the vertical dimension (z-axis) rather than horizontal plane. This dimensional change allows multiple memory cells to be stacked above each other, significantly reducing the horizontal footprint while utilizing the vertical space for storage capacity.

The patent implements nested structures where charge storage elements (such as charge trapping layers or floating gates) are embedded within the vertical memory cell stack. The insulating materials and conductive layers are nested in alternating tiers, with each layer contained within the vertical structure, creating a compact nested arrangement that maximizes storage density within the vertical thickness.

The patent divides the memory device into segmented vertical strings, where each string consists of discrete memory cells separated by insulating materials. The alternating tiers of conductive and insulating materials create naturally segmented structures that are easier to fabricate and control individually, reducing overall fabrication complexity while maintaining high packing density.

The patent utilizes parameter changes in material deposition and etching processes to achieve the vertical structure. By controlling deposition thickness, etch selectivity, and layer sequencing, the complex vertical architecture is fabricated through standardized semiconductor manufacturing parameters, making the complex structure manufacturable with existing process capabilities.