Interconnecting Die Chiplet Package for High-Bandwidth Integration
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Solution Overview
Problem
Conventional processes for integrating IC dies in chip packages involve complex steps leading to low yield and high costs, particularly in achieving high bandwidth communications.
Innovation Solution
A multi-die device with IC dies connected by an interconnecting die, utilizing simplified interconnecting interfaces formed with fewer polymer and metal layers, and incorporating conductive pillars and interconnecting die structures for efficient vertical and lateral connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional processes are used for integrating IC dies, interconnected dies, and RDLs, then high bandwidth communications can be achieved, but the manufacturing process becomes complex resulting in low yield and high cost
Solution Approach 1:
The patent segments the integration process into distinct modules: IC dies, interconnected dies, and RDLs are designed as separate functional units that can be independently fabricated and tested. This segmentation allows each component to be optimized independently while maintaining the overall system's high bandwidth capability, reducing the complexity of the overall integration process.
Solution Approach 2:
The patent applies preliminary action by pre-configuring the interconnected dies and RDLs with necessary conductive structures and interconnect interfaces before final assembly. This advance preparation simplifies the subsequent integration steps, as components are ready-to-connect with pre-formed electrical pathways, thereby reducing manufacturing complexity and improving yield.
2Adaptability or versatility
If conventional processes are used for integrating IC dies, interconnected dies, and RDLs, then functional integration can be achieved, but manufacturing cost increases due to many process steps
Solution Approach 1:
The patent merges multiple functions into unified structures: interconnected dies serve both as communication bridges and as support for RDLs; conductive pillars integrate electrical connection and mechanical support functions. This consolidation reduces the number of discrete components and process steps required, thereby lowering manufacturing cost while maintaining functional integration.
Solution Approach 2:
The patent designs universal interconnect structures that can accommodate different IC die types and configurations. The RDLs and conductive pillars are configured to provide both electrical interconnection and structural support across multiple applications, enabling the same manufacturing process to produce various functional integrations without requiring additional specialized steps, thus reducing overall manufacturing cost.
3Adaptability or versatility
If multiple process steps are used for integrating IC dies and RDLs, then complete functionality can be achieved, but manufacturing yield decreases
Solution Approach 1:
The patent performs preliminary configuration of conductive structures and interconnect interfaces on interconnected dies and RDLs before final assembly. This advance preparation ensures that components are ready for direct connection, eliminating the need for additional alignment and bonding steps during integration, thereby reducing the total number of process steps and improving manufacturing yield while maintaining complete functionality.
Solution Approach 2:
The patent introduces interconnected dies as intermediary structures that mediate between IC dies and RDLs. These intermediaries pre-establish the necessary electrical and mechanical connections, simplifying the integration process and reducing the number of direct connection steps required between IC dies and RDLs, thus improving yield while preserving complete system functionality.
Data Source
AI summary
Disclosed herein is a multi-die device, and an integrated chip package assembly having the multi-die device. The multi-die device includes a first IC die and a second IC die disposed at a same tier; a first conductive pillar coupled with the first IC die; a second conductive pillar coupled with the second IC die; and an interconnecting die disposed between the first conductive pillar and the second conductive pillar and configured to couple with the first IC die and the second IC die. The multi-die device further includes a first interconnecting interface disposed on the first IC die; a second interconnecting interface disposed on the second IC die, the first interconnecting interface and the second interconnecting interface being separated by a molding material.