Semiconductor Interconnection Alignment via Coordinate Compensation
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Solution Overview
Problem
The existing interconnection structure fabrication method often results in plugs deviating from their intended position, leading to bridging or short-circuiting between semiconductor components, which affects device performance and yield due to overlay shifts and stacking offsets during the photolithography process.
Innovation Solution
A method involving the use of alignment marks and layers to obtain reference and measurement coordinates, calculate wafer coordinates, and adjust the wafer position to accurately align interconnection structures, incorporating a compensation system to account for stacking offsets and ensure precise alignment between the first and second to-be-connected members.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography alignment methods are used, then the fabrication process is simple, but the plug position deviates from the intended location causing bridging or short-circuiting
Solution Approach 1:
Alignment marks are formed in advance during the first conductive layer patterning process, and their coordinates are obtained before subsequent patterning steps. This preliminary measurement and coordinate acquisition enables predictive alignment compensation for the second opening position, preventing plug deviation before it occurs
Solution Approach 2:
The system measures the actual positions of alignment marks using coordinates obtained from multiple layers, calculates the deviation between expected and actual positions, and uses this feedback information to compensate for alignment errors in subsequent patterning steps, thereby improving plug position accuracy
2Reliability
If multiple etching processes are performed to form contact holes and trenches, then the interconnection structure is complete, but the accumulation of alignment errors causes plug deviation
Solution Approach 1:
Alignment marks are measured at multiple stages (first conductive layer and first mask layer) to obtain coordinate data that reflects cumulative alignment errors. This feedback is used to calculate and compensate for stacking offsets, preventing error accumulation from affecting the final plug position and device reliability
Solution Approach 2:
Alignment marks serve as intermediary reference elements that link different layers and patterning steps together. By measuring these intermediary marks and using their coordinates to calculate wafer coordinates and compensation values, the system maintains precise alignment relationships across multiple etching and patterning processes
3Productivity
If wafer position is not adjusted for stacking offsets, then the fabrication process is efficient, but bridging or short-circuiting occurs between adjacent components
Solution Approach 1:
Wafer coordinates characterizing position deviation are obtained in advance before forming the second opening. Adjustment compensation values are calculated based on these coordinates and stacking offset measurements from preceding wafers, allowing the wafer position to be pre-adjusted to compensate for anticipated alignment errors, thus maintaining both efficiency and precision
Data Source
AI summary
In some embodiments, an interconnection structure, an exposure alignment system, and a fabricating method thereof are provided. The method comprises: providing a wafer, forming a first to-be-connected member and multiple first alignment members in a first conductive layer; form a first opening and multiple second alignment members in a first mask layer, the first opening is used to define a position of a second to-be-connected member; based on reference and measurement coordinates of the first alignment members, and reference coordinates and measurement coordinates of the second alignment members, obtaining wafer coordinates for characterizing a position deviation of the wafer; obtaining adjustment compensation values according to stacking offsets of a preceding wafer; adjusting a position of the wafer; forming the interconnection structure in a first dielectric layer and a second dielectric layer to electrically interconnect the first to-be-connected member and the second to-be-connected member.