Interconnection Structure Preventing Cauliflower Defects
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Solution Overview
Problem
The existing methods for manufacturing interconnection structures in semiconductor technologies often result in cauliflower defects and voids due to over-growth and surface property issues, leading to short circuits and device failures.
Innovation Solution
A method involving a dual-damascene through hole structure where the upper surface of the second metal layer is made lower than the exposed part of the through hole structural layer, preventing over-growth and voids by etching the through hole structural layer and removing the hard mask layer to alleviate surface property impacts during deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a selective deposition process is used to form a cobalt layer in through holes, then the cobalt layer can be deposited selectively, but over-growth occurs causing cauliflower defects and short circuits
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer (CMP process) before the selective deposition of the cobalt layer. This planarization step creates a flat surface that prevents over-growth during subsequent deposition, thereby avoiding cauliflower defects while maintaining the selective deposition capability.
2Strength
If a TiN hard mask layer is formed on the top of the semiconductor structure, then the hard mask provides structural support, but surface property issues cause voids in the deposited cobalt layer
Solution Approach 1:
The patent applies the taking out principle by removing the TiN hard mask layer after the copper layer is formed. This extraction eliminates the surface property issues that caused voids in the cobalt layer, while the hard mask's structural support function was already fulfilled during the previous processing steps.
3Quantity of substance
If the cobalt layer is deposited to fill through holes, then the through holes are completely filled, but over-growth causes connection between different through holes leading to short circuits
Solution Approach 1:
The patent applies preliminary action by performing CMP planarization before cobalt deposition to create a flat surface. This preliminary step ensures that the cobalt layer deposits uniformly without over-growth into adjacent through holes, maintaining complete filling while preventing short circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents cauliflower defects and voids, enhancing the reliability of the interconnection structure by ensuring proper metal layer deposition and preventing subsequent defects during the formation of the third metal layer.
Implementation Method 1
a second metal layer is deposited in the second through hole and the third through hole
Implementation Method 2
the part of the through hole structural layer between the second through hole and the third through hole is etched
Data Source
AI summary
The present disclosure teaches interconnection structures and methods for manufacturing the same. In one implementation, a method may include: providing a substrate structure, including: a substrate, an interlayer dielectric layer on the substrate, a plurality of first through holes running through the interlayer dielectric layer, and a first metal layer filling the plurality of first through holes; forming a through hole structural layer on the substrate structure, where a dual-damascene through hole structure included in the through hole structural layer includes: a second through hole and a third through hole in the through hole structural layer, and an opening on the second through hole and the third through hole, and a part of the through hole structural layer between the second through hole and the third through hole is exposed in the opening; filling a second metal layer in the second through hole and the third through hole, where an upper surface of the second metal layer is lower than an upper surface of the part of the through hole structural layer; etching the part of the through hole structural layer so that the upper surface of the part is lower than the upper surface of the second metal layer; and forming, in the opening, a third metal layer connected to the second metal layer. The present disclosure addresses a problem of a cauliflower defect in the prior art.