Semiconductor Interconnection Structure with Conductor Pillar
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Solution Overview
Problem
Current interconnection systems in semiconductor chips require additional layers and space, leading to increased die size and inefficient signal transmission due to the inability to directly connect gate terminals to M2 without bypassing M1, and lack self-alignment capabilities between Via1 and contacts.
Innovation Solution
An interconnection structure and method that includes a first dielectric layer, a conductor pillar, and an upper dielectric layer, where the conductor pillar connects to an upper conduction layer but disconnects from the first conduction layer, allowing for direct connections between gate or diffusion regions and M2 without transitional layers, and enabling self-alignment of Via1 and contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a traditional interconnection system with multiple layers (M1, M2, M3) and via structures is used, then signal transmission can be achieved, but the die size increases and the wiring complexity increases
Solution Approach 1:
The patent transitions from a planar interconnection architecture to a three-dimensional stacked architecture. Multiple interconnection layers (first conduction layer, second conduction layer, third conduction layer) are stacked vertically with dielectric layers in between, enabling signals to travel through the vertical dimension rather than only horizontally across the die. This dimensional change reduces the required die area while maintaining signal transmission capabilities.
Solution Approach 2:
The patent implements a nested structure where conductor pillars are embedded within dielectric layers, which are in turn embedded within other dielectric layers, forming a stacked configuration. Each layer is nested within the previous layer's structure, creating a compact vertical arrangement that reduces overall die size while maintaining multiple interconnection pathways.
2Productivity
If additional interconnection layers are added to facilitate signal transmission, then signal transmission efficiency improves, but the die size enlarges
Solution Approach 1:
The patent utilizes vertical stacking of conduction layers separated by dielectric layers to create multiple signal transmission pathways in the vertical dimension. This allows signals to be transmitted more efficiently through the chip without requiring additional horizontal space, thus improving productivity without increasing die size.
Solution Approach 2:
The patent employs thin dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) that separate the conduction layers while occupying minimal vertical space. These thin film structures enable multiple interconnection layers to be stacked closely together, maximizing signal transmission efficiency within a compact vertical footprint.
3Manufacturing precision
If conventional via structures are used to connect interconnection layers, then vertical connections are achieved, but self-alignment between via and contact is not possible
Solution Approach 1:
The patent forms conductor pillars within dielectric layers at predetermined locations before forming the subsequent dielectric and conduction layers. These pre-positioned conductor pillars serve as alignment references that enable automatic self-alignment of subsequent via holes and contact structures, eliminating the need for complex alignment processes and improving manufacturing precision.
Solution Approach 2:
The patent implements self-alignment mechanisms where the conductor pillars and previously formed structures serve as their own alignment references. The manufacturing process automatically aligns subsequent layers to these existing structures without requiring additional alignment steps or external reference marks, thereby improving precision while reducing process complexity.
Data Source
AI summary
This invention provides a manufacture method for an interconnection structure including the following steps: forming a first dielectric layer over a first conductive terminal; forming a conductor pillar penetrating through the first dielectric layer, wherein the conductor pillar is electrically connected to the first conductive terminal but not electrically connected to a first conduction layer over the first dielectric layer; forming an upper dielectric layer over the first conduction layer; and forming an upper conduction layer over the upper dielectric layer, wherein the conductor pillar is connected to the upper conduction layer.