Semiconductor Interconnection Structure for Flatness and Etch Selectivity
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving reliable interconnection structures that maintain flatness and prevent warpage, due to limitations in etch selectivity and fabrication complexity, which affect the durability and reliability of the interconnection patterns.
Innovation Solution
The proposed solution involves a stacked structure of dielectric layers and hardmask patterns with etch selectivity, where silicon oxide layers with varying densities and compositions are used to control warpage, and the hardmask patterns are formed from dielectric materials to simplify fabrication and enhance mechanical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If conventional interconnection structures are used, then fabrication can proceed with standard processes, but warpage occurs and flatness is compromised
Solution Approach 1:
The patent changes the material parameters of the hardmask layer by using silicon oxide with controlled density (ranging from 2.0 g/cm³ to 2.2 g/cm³) and specific thickness (50 nm to 150 nm). This parameter optimization allows the hardmask layer to serve dual functions: maintaining etch selectivity for reliable interconnection patterning and providing sufficient mechanical support to prevent warpage, thereby achieving both flatness and reliability improvements
Solution Approach 2:
The patent employs a composite dielectric structure consisting of multiple layers with different materials and properties: a first dielectric layer (e.g., polyimide or BCB), a silicon oxide hardmask layer with specific density, and a second dielectric layer. This composite structure combines the advantages of each material to achieve both mechanical stability (preventing warpage) and fabrication reliability (maintaining etch selectivity), thus resolving the contradiction between flatness and reliability
2Manufacturing precision
If hardmask layers are used to maintain selectivity, then etching precision is improved, but fabrication complexity increases
Solution Approach 1:
The silicon oxide hardmask layer is designed to perform multiple functions simultaneously: it provides etch selectivity for precise interconnection patterning, serves as a mechanical reinforcement layer to prevent warpage, and acts as a diffusion barrier. By consolidating these functions into a single layer with optimized parameters, the patent reduces fabrication complexity while maintaining high etching precision
Solution Approach 2:
The patent applies local quality by positioning the silicon oxide hardmask layer specifically at critical interfaces where etch selectivity is most needed, such as between the interconnection pattern and the dielectric layers. The layer's thickness and density are locally optimized to provide maximum etching precision without adding unnecessary complexity to the overall structure
3Shape
If multiple dielectric layers are stacked to control warpage, then flatness is improved, but manufacturing complexity increases
Solution Approach 1:
The patent optimizes the parameters of the silicon oxide hardmask layer (thickness: 50-150 nm, density: 2.0-2.2 g/cm³) to achieve the desired flatness control within a constrained parameter space. This focused parameter optimization allows for effective warpage control while maintaining compatibility with existing manufacturing processes, thus improving ease of manufacture compared to unoptimized multi-layer approaches
Data Source
AI summary
Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.