Interconnection Lane Reassignment for Parallel Bus Skew Reduction
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Solution Overview
Problem
Current memory systems face limitations in size, performance, and cost due to power consumption, cooling capacity, response time, and data skew issues, particularly in high-speed circuits where signal propagation delay and manufacturing tolerances impact realizable speeds and upgradeability.
Innovation Solution
An interconnection system with a bus having multiple signal lines that exchanges data bits between nodes, compensating for differential time delays by reassigning data lanes to minimize cumulative time delays, using configurable switches and software to manage data skew and optimize transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted on multiple signal lines in parallel, then transmission speed is improved, but data skew between lines increases
Solution Approach 1:
The patent applies dynamic lane assignment where the mapping between data lanes and signal lines is not fixed but can be adjusted based on measured propagation delays. The system dynamically reassigns data lanes to different signal lines to compensate for skew, transforming a static connection into an adaptive one that responds to actual transmission characteristics.
Solution Approach 2:
The system changes the parameter of lane-to-line mapping by measuring actual propagation delays and reassigning data lanes to different signal lines. This parameter change compensates for manufacturing variations in line lengths and characteristics, allowing the system to maintain data integrity despite physical imperfections.
2Adaptability or versatility
If signal lines are made longer to connect distant nodes, then system scalability is improved, but cumulative time delay increases
Solution Approach 1:
The system measures cumulative time delays across multiple hops and reassigns data lanes to compensate for the accumulated skew. By dynamically adjusting the lane-to-line mapping based on measured delays, the system can extend the network to distant nodes without suffering from unbounded skew accumulation.
Solution Approach 2:
The patent implements a feedback mechanism where propagation delays are measured and used to adjust lane assignments. This feedback loop allows the system to adapt to varying path lengths and delay characteristics, enabling scalable network expansion while maintaining synchronization.
3Device complexity
If fixed lane assignment is used to simplify system design, then device complexity is reduced, but data skew management becomes difficult
Solution Approach 1:
The system performs self-characterization by automatically measuring propagation delays on each signal line and using this information to optimize lane assignments. This self-service approach eliminates the need for manual characterization and complex pre-configured assignments, allowing the system to adapt to its own physical characteristics.
Solution Approach 2:
The system changes the lane-to-line mapping parameter based on measured delays, transforming a potentially complex fixed assignment problem into a dynamic optimization that adapts to actual physical conditions. This parameter adjustment simplifies the overall design by eliminating the need for precise manual configuration.
Data Source
AI summary
An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.