Interconnection Structure With Selective Dielectric for Tighter Wiring Spacing
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Solution Overview
Problem
The challenge in reducing the distance between metal wirings in integrated circuit devices is hindered by the limitations of the photolithography process, which also complicates the reduction of metal wiring resistance.
Innovation Solution
An interconnection structure is developed with a dielectric layer having etch selectivity, allowing for a reduced separation distance between conductive layers by using silicon nitride, silicon oxynitride, or other materials with etch selectivity, enabling closer spacing of metal wirings while maintaining low resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the photolithography process is used to form metal wirings, then the manufacturing process is simple and well-established, but the distance between metal wirings cannot be reduced further due to process limitations
Solution Approach 1:
The patent divides the interlayer insulating layer into multiple trenches (first trench, second trench, third trench) with different widths and spacing. The first conductive layer is formed in the first trench with a larger width, while the second and third conductive layers are formed in narrower trenches with different spacing. This segmentation allows different regions to have optimized wiring distances and resistance characteristics independently, overcoming the uniform limitations of photolithography.
Solution Approach 2:
The patent applies local quality by creating trenches with non-uniform widths and spacing arrangements. The first trench has a different width compared to the second and third trenches, and the spacing between trenches is optimized locally. This allows the interconnection structure to achieve reduced wiring resistance in critical areas while maintaining appropriate spacing in other areas, addressing the specific need to reduce metal wiring distance without uniformly complicating the entire manufacturing process.
2Reliability
If the distance between metal wirings is reduced to lower resistance, then the wiring resistance decreases, but the photolithography process limitation prevents further reduction
Solution Approach 1:
The patent employs asymmetry by forming trenches with different widths and spacing arrangements. The first trench has a larger width than the second and third trenches, and the spacing between the first and second trenches differs from the spacing between the second and third trenches. This asymmetric design allows critical wiring paths to have reduced distances for lower resistance, while other areas maintain appropriate spacing, thereby improving wiring reliability without being uniformly constrained by photolithography limitations.
Solution Approach 2:
The patent transitions from a two-dimensional planar wiring layout to a three-dimensional trench-based structure with varying depths and widths. By forming trenches at different levels and with different cross-sectional dimensions, the patent achieves reduced wiring resistance through vertical and lateral dimension optimization, overcoming the planar photolithography limitations.
3Reliability
If uniform trenches are used in the interlayer insulating layer, then the manufacturing process is simple, but the wiring resistance cannot be optimized in different regions
Solution Approach 1:
The patent applies local quality by creating trenches with non-uniform widths and spacing arrangements. The first trench has a different width compared to the second and third trenches, and the spacing between trenches is optimized locally. This allows the interconnection structure to achieve reduced wiring resistance in critical areas while maintaining appropriate spacing in other areas, addressing the specific need to reduce metal wiring distance without uniformly complicating the entire manufacturing process.
Solution Approach 2:
The patent divides the interlayer insulating layer into multiple trenches (first trench, second trench, third trench) with different widths and spacing. The first conductive layer is formed in the first trench with a larger width, while the second and third conductive layers are formed in narrower trenches with different spacing. This segmentation allows different regions to have optimized wiring distances and resistance characteristics independently, overcoming the uniform limitations of photolithography.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the separation distance between metal wirings, overcoming photolithography limitations and enhancing the interconnection structure's efficiency and performance.
Implementation Method 1
a dielectric layer formed between the first conductive layer and the second conductive layer, wherein a portion of interlayer insulating layer is disposed between the second conductive layer and the third conductive layer
Data Source
AI summary
An integrated circuit device includes an interconnection structure that includes: an interlayer insulating layer arranged on a substrate and having a plurality of trenches; a first conductive layer formed inside a first trench of the plurality of trenches; a second conductive layer formed inside a second trench of the plurality of trenches, wherein the second trench is spaced apart from the first trench; a third conductive layer formed inside a third trench of the plurality of trenches, wherein the third trench is spaced apart from the second trench; and a dielectric layer formed between the first conductive layer and the second conductive layer, wherein a portion of interlayer insulating layer is disposed between the second conductive layer and the third conductive layer, and wherein a first width of the first conductive layer is greater than a second width of the second conductive layer.