Interconnection Module Substrate for Multi-Pitch Semiconductor Packaging
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Solution Overview
Problem
Existing semiconductor package substrates face challenges in accommodating chips with multiple electrode pitches due to limited responsiveness and pattern resolution, making them difficult to design and manufacture for various package designs while ensuring durability.
Innovation Solution
The development of an interconnection module substrate with a plurality of via-defining structures and interconnection bridge members, where the substrate material layer embeds these structures to form a single substrate shape, allowing for flexibility in electrode pitch responsiveness and ease of manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a silicon bridge is used in EMIB technology to reduce board area and package height, then the package size and power consumption are reduced, but the substrate cannot adequately respond to different electrode pitches and pattern resolution requirements
Solution Approach 1:
The substrate is divided into multiple regions with different electrode pitch patterns. The via-defining structures are arranged in different patterns corresponding to different electrode pitches, allowing each region to be optimized for specific chip types while maintaining a compact overall substrate size.
Solution Approach 2:
The patent introduces vertical via-defining structures that extend through the substrate thickness, adding a vertical dimension to the interconnection architecture. This enables three-dimensional routing of electrical connections, allowing different electrode pitches to be accommodated by varying via positions and orientations in the vertical dimension rather than only in the horizontal plane.
2Area of stationary object
If a silicon bridge is used to reduce package size, then manufacturing complexity increases and durability decreases due to deformation issues
Solution Approach 1:
The via-defining structures are designed with locally optimized geometries and materials suited to specific regions of the substrate. Different areas can have different via diameters, depths, and materials, allowing each region to be manufactured using appropriate processes while maintaining overall compactness.
Solution Approach 2:
The via-defining structures are formed as pre-configured elements within the substrate before chip mounting. This preliminary formation of interconnection pathways simplifies subsequent assembly processes and reduces manufacturing complexity compared to forming connections after substrate assembly.
3Length of stationary object
If a silicon bridge is used to reduce package height, then the substrate lacks durability due to deformation
Solution Approach 1:
The substrate employs composite material construction combining multiple materials with complementary properties. The via-defining structures may use different materials than the substrate matrix, creating a composite structure that maintains mechanical strength and resistance to deformation while achieving reduced package height through optimized material properties.
Solution Approach 2:
The via-defining structures are designed with built-in mechanical support features that provide structural reinforcement before deformation issues can occur. The three-dimensional via structures act as preemptive structural elements that prevent deformation under subsequent mechanical or thermal stress during packaging and operation.
Data Source
AI summary
Disclosed are an interconnection module substrate for a semiconductor package, a semiconductor package device including the same, and manufacturing methods thereof. The interconnection module substrate includes a plurality of via-defining structures disposed spaced apart from each other in a horizontal direction, each of the plurality of via-defining structures including a substrate material unit and a conductive via element extending through the substrate material unit in a vertical direction, at least one interconnection bridge member disposed spaced apart from or adjacent to the plurality of via-defining structures in the horizontal direction, and a substrate material layer embedded in the space between and around the plurality of via-defining structures and the interconnection bridge member to form a single substrate shape together therewith, the substrate material layer being configured to expose the plurality of via-defining structures and the interconnection bridge member.


