Electronic Package Interconnections with Different Melting Temperatures
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Solution Overview
Problem
Conventional packaging methods for power modules, such as those used in automotive applications, face challenges in achieving high spatial accuracy and reliability due to simultaneous melting of interconnections during the packaging process, leading to issues like gap formation and positional inaccuracies.
Innovation Solution
The implementation of interconnections with different melting or re-melting temperatures, specifically configuring at least one interconnection to have a higher melting point than the others, prevents simultaneous melting and ensures reliable packaging by avoiding reflow and positional inaccuracies, using materials like high-temperature stable SnSb solder, ductile Pb solder, and welding techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging methods use interconnections with the same melting temperature, then the packaging process is simpler, but simultaneous melting occurs leading to gap formation and positional inaccuracies
Solution Approach 1:
The patent applies parameter changes by varying the melting temperatures of different interconnections. Specifically, it uses a first interconnection material with a first melting temperature and a second interconnection material with a second melting temperature that is higher than the first. This allows sequential melting and solidification during the packaging process, preventing simultaneous melting and the associated reliability issues such as gap formation and positional inaccuracies.
2Manufacturing precision
If interconnections with different melting temperatures are used, then spatial accuracy and reliability are improved, but material selection and process complexity increase
Solution Approach 1:
The patent implements parameter changes by selecting interconnection materials with different melting temperatures. The first interconnection uses material with a lower melting point that solidifies first, establishing a stable foundation. The second interconnection uses material with a higher melting point that solidifies later, achieving precise spatial positioning without disrupting the first interconnection's integrity.
3Productivity
If all interconnections melt simultaneously during packaging, then the process is faster, but reliability issues such as gap formation and positional inaccuracy occur
Solution Approach 1:
The patent applies preliminary action by designing the interconnection structure so that the first interconnection material melts and solidifies before the second interconnection material. This sequential process ensures that the first interconnection is already solid and stable when the second interconnection is being formed, preventing reliability issues such as gap formation and positional inaccuracies that would occur if both melted simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and thermal performance of the package by preventing simultaneous melting of interconnections, maintaining spatial accuracy, and improving thermal conductivity, thus addressing the limitations of conventional packaging methods.
Implementation Method 1
the first interconnection is configured to have another melting (or re-melting) temperature than the second interconnection
Implementation Method 2
a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip
Data Source
AI summary
A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.