Interdigital Gate Thin Film Transistor Area Reduction
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Solution Overview
Problem
Conventional thin film transistors occupy a large area, leading to increased manufacturing costs in liquid crystal displays.
Innovation Solution
A thin film transistor array substrate design featuring an interdigital light-shielding layer, buffer layer, channel layer, insulating layers, and electrodes, with an electrically conductive connection between the interdigital gate and light-shielding layer, optimizing the channel width and reducing the overall device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional TFT device structure is used, then the device can be manufactured with standard processes, but the area occupied by the TFT device is too large resulting in increased manufacturing cost
Solution Approach 1:
The patent transitions from a conventional planar gate structure to an interdigital gate structure where gate electrodes and light-shielding layers are arranged in interdigitated fingers. This dimensional reorganization allows the channel to extend underneath the gate structure, effectively increasing the channel width without increasing the lateral footprint of the device, thereby reducing the area occupied by the TFT while maintaining manufacturing feasibility
Solution Approach 2:
The patent implements nesting by positioning the channel layer to extend underneath the interdigital gate structure, effectively nesting the channel formation process within the gate structure footprint. The gate electrodes and light-shielding layers are nested in an interdigitated arrangement, allowing multiple functional elements to occupy overlapping spatial regions, which reduces the overall device area while maintaining all necessary functions
Data Source
AI summary
The present invention discloses a thin film transistor array substrate, a manufacturing method thereof, and a display panel. In the present invention, a width of the channel is increased by cooperation of an electrically connection between the interdigital gate and the interdigital light-shielding layer with design of the interdigital gate. When a width/length ratio (W/L) of the channels in a single thin film crystal device is maintained constant, an increase in the channel width allows the width of the channel layer occupied by the channels to be reduced while maintaining the total width of the channels in the single thin film transistor constant, thereby reducing the area occupied by the single thin film transistor device.