Inter-digital Lead Frame for High Current Flip Chip Power Devices
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Solution Overview
Problem
Conventional methods for reducing interconnection resistance in integrated circuit devices, such as using low resistance materials or flip chip interconnection ball grid array techniques, are insufficient for high-power consumer electronics, leading to increased package size and high production costs, and do not effectively handle large current requirements.
Innovation Solution
A lead frame structure with finger-shaped electrical leads arranged in inter-digital patterns to support semiconductor dies, allowing for low interconnection resistance and high current handling, achieved by bonding flip chip dies to the lead frame and encapsulating them in a molding material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional wire bonding or parallel device placement is used to interconnect high power integrated circuits, then interconnection resistance is reduced to some extent, but package size increases and parasitic inductance is introduced
Solution Approach 1:
The electrical leads are segmented into multiple finger-shaped structures that extend outward from the central lead body. This segmentation increases the effective bonding area between the die and lead frame, reducing interconnection resistance without requiring a larger package footprint. The fingers are distributed across the die surface to minimize current density and reduce overall resistance.
Solution Approach 2:
The interconnection structure transitions from a planar two-dimensional layout to a three-dimensional configuration with finger-shaped leads extending in multiple directions. This dimensional change allows for increased bonding area and better current distribution within the same package area, effectively reducing interconnection resistance without increasing package size.
2Loss of energy
If low resistance materials such as gold are used to reduce interconnection resistance, then current carrying capability is improved, but production cost increases significantly
Solution Approach 1:
The finger-shaped lead structures concentrate the low-resistance interconnection function at specific local bonding points between the die and lead frame, rather than requiring low-resistance materials throughout the entire package. This localized approach reduces material costs while maintaining low interconnection resistance where it is most critical for current carrying capability.
Solution Approach 2:
The invention changes the geometric parameters of the lead structures (creating finger-shaped extensions) rather than changing the material parameters (using expensive low-resistance materials). This parameter change achieves reduced interconnection resistance through increased surface area and improved bonding geometry, maintaining cost-effectiveness while improving electrical performance.
3Loss of energy
If flip chip BGA techniques are used to interconnect high power dies to lead frame, then interconnection resistance is reduced, but the resistance is still insufficient for very high current applications
Solution Approach 1:
The invention merges the advantages of flip chip bonding with traditional lead frame structures by combining the low-resistance interconnection of flip chip techniques with the robust current carrying capability of extended finger-shaped leads. This hybrid approach achieves lower interconnection resistance than conventional flip chip BGA while maintaining reliability for high current applications through the enhanced lead geometry.
Solution Approach 2:
The finger-shaped lead structures are pre-configured on the lead frame before die attachment, creating optimized current distribution pathways in advance. This preliminary configuration ensures that high current is evenly distributed across multiple bonding points, preventing localized overheating and improving reliability for very high current applications before the actual bonding process occurs.
Data Source
AI summary
A lead frame structure for supporting a semiconductor die is disclosed that includes at least two electrical leads each having a plurality of finger shaped structures unilaterally extending outward from the at least two electrical leads. The electrical leads are arranged so that the plurality of finger shaped structures forms inter-digital patterns where the semiconductor dies are bonded to the lead frame structure.