Interdigitated Capacitor Layout for High-Resolution OLED Displays

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Solution Overview

Problem

Existing head-mounted displays face challenges in achieving high-resolution images due to limitations in display technology, particularly with organic light-emitting diodes (OLEDs) used in head-mounted displays, which struggle to provide the necessary resolution for virtual and augmented reality applications.

Innovation Solution

The display device incorporates a specific capacitor design with sub-capacitor electrodes arranged in a particular configuration to enhance the electrical properties of the display, including a first capacitor electrode connected to a first node and a second capacitor electrode connected to a second node, with sub-capacitor electrodes at the same layer, and outermost sub-capacitor electrodes positioned to optimize electrical connections and improve image quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional capacitor design is used in display devices, then device complexity is reduced, but image quality and resolution are insufficient for head-mounted display applications

Engineering Contradiction:
Improveimage qualityVSAvoidcapacitor structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The capacitor electrode is divided into multiple sub-capacitor electrodes (first sub-capacitor electrodes and second sub-capacitor electrodes) arranged in an interdigitated pattern. This segmentation increases the effective capacitance area without proportionally increasing device footprint, thereby improving image quality and resolution while managing device complexity through systematic subdivision of the electrode structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sub-capacitor electrodes are arranged in multiple layers (first sub-capacitor electrodes at a first level, second sub-capacitor electrodes at a second level) creating a three-dimensional interdigitated structure. This dimensional arrangement increases the capacitance area in the vertical dimension, enabling higher resolution display performance without proportionally increasing the horizontal device footprint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If display resolution is increased for head-mounted display applications, then image quality improves, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvedisplay resolutionVSAvoidmanufacturing difficulty
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The capacitor electrode is segmented into multiple sub-capacitor electrodes that can be manufactured using standard photolithography and deposition processes. This segmentation allows for incremental manufacturing complexity that matches current fabrication capabilities, enabling high resolution display manufacturing without requiring fundamentally new manufacturing techniques

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sub-capacitor electrodes are arranged in a nested, interdigitated pattern where first and second sub-capacitor electrodes alternate and interlock. This nested arrangement maximizes the use of available space and allows for systematic manufacturing through sequential deposition steps, making high-resolution displays more manufacturable

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20250374764A1Display device
Publication Date: 2025.12.04 SAMSUNG DISPLAY CO LTD
  • US20250374764A1 patent drawing
  • US20250374764A1 patent drawing
  • US20250374764A1 patent drawing

AI summary

The present disclosure relates to a display device with improved image quality. The display device may include a substrate, a light-emitting element above the substrate, a transistor connected to the light-emitting element, a first node connected to a gate electrode of the transistor, and a capacitor connected between the first node and a second node, and including a first capacitor electrode connected to the first node and including first sub-capacitor electrodes, and a second capacitor electrode connected to the second node, and including second sub-capacitor electrodes at a same layer as the first sub-capacitor electrodes, wherein one of the first sub-capacitor electrodes is between adjacent ones of the second sub-capacitor electrodes.