Interdigitated Gate Trenches for Power MOSFET Loss Optimization
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Solution Overview
Problem
Current trench power MOSFETs face challenges in optimizing both conduction and switching losses while maintaining high voltage blocking capability and low on-state resistance, particularly in automotive and industrial electronics applications.
Innovation Solution
The semiconductor device incorporates a unique layout with a first and second gate trench separated by a mesa, featuring interdigitated fingers and a comb-like structure, where the gate electrode in one trench is electrically connected to the source potential instead of the gate potential, optimizing the device's efficiency and reducing gate charge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional trench structure is used, then the manufacturing process is simple, but the device efficiency is insufficient due to inability to optimize both conduction and switching losses
Solution Approach 1:
The gate trench is divided into multiple sections (first sections extending in first direction, second sections connecting adjacent first sections) arranged in an interdigitated pattern with source trenches. This segmentation allows independent optimization of different trench regions for both conduction and switching performance without requiring complete structural redesign.
Solution Approach 2:
Different sections of the gate trench are positioned at different locations relative to source trenches (some sections disposed opposite to source trench sections, others between adjacent source trench sections). This creates local variations in electrical characteristics that optimize both conduction loss in some regions and switching loss in others, achieving overall energy efficiency improvement.
2Loss of energy
If the gate trench is positioned to optimize electrical characteristics, then device efficiency improves, but the feature size increases
Solution Approach 1:
The gate trench structure extends in multiple directions (first direction for first sections, second direction for second sections connecting them), creating a two-dimensional interdigitated pattern. This multi-directional arrangement optimizes electrical characteristics for switching loss reduction while maintaining compact overall footprint, avoiding single-direction elongation that would increase feature size.
3Loss of energy
If the gate trench is positioned to reduce conduction loss, then on-state resistance decreases, but the voltage blocking capability is compromised
Solution Approach 1:
The gate trench is segmented into multiple sections with different positional relationships to source trenches. Some sections are disposed opposite to source trench sections (optimizing for conduction loss reduction), while the overall interdigitated structure maintains adequate spacing and field distribution (preserving voltage blocking capability). This segmentation allows simultaneous optimization of conflicting electrical requirements.
Data Source
AI summary
A transistor device includes a first trench and a second trench arranged in a comb-like structure, first sections of the first and second trenches corresponding to teeth of the comb-like structure and second sections of the first and second trenches corresponding to opposing shafts of the comb-like structure. The arrangement of the first trench and the second trench forms a pattern of interdigitated fingers. Transistor cells of the transistor device are disposed between single fingers of the first and second trenches. A semiconductor mesa separates the first trench and the second trench from each other. A gate electrode in the first trench or a gate electrode in the second trench is electrically connected to a source potential instead of a gate potential to decrease a gate charge of the transistor device.