Interdigitated Planar Inductor Terminals for Series Resistance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Designing integrated circuits with high-quality inductors is challenging due to the difficulty in minimizing series resistance, which affects the quality factor and efficiency of resonant circuits, particularly in portable applications where power dissipation is a concern.
Innovation Solution
The approach involves forming a conductive loop with interdigitated fingers and a serpentine gap in an ultra-thick conductive layer, coupled with a lower resistivity material, and using multiple conductive vias to reduce series resistance and enhance current routing, thereby increasing the quality factor of the inductor system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inductor designs are used in integrated circuits, then the device can be manufactured with standard processes, but the series resistance is high which reduces the quality factor
Solution Approach 1:
The patent transitions from planar 2D conductive traces to a 3D vertically-stacked conductive structure. Multiple conductive layers are stacked vertically with vias connecting them, creating a three-dimensional current path that reduces series resistance while maintaining a compact footprint suitable for integrated circuit manufacturing.
Solution Approach 2:
The inductor employs composite conductive structures combining multiple conductive layers of different materials and thicknesses. The first conductive layer has higher thickness and lower resistivity than the second conductive layer, creating a composite structure that optimizes both electrical performance and manufacturability.
2Loss of energy
If the conductive loop uses a single thick conductive layer, then series resistance is reduced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The conductive structure is segmented into multiple discrete conductive layers (first conductive layer and second conductive layer) connected by vias. This segmentation allows each layer to be optimized independently for thickness and resistivity while maintaining overall manufacturability through standard multi-layer IC fabrication processes.
Solution Approach 2:
Different regions of the conductive structure have different properties: the first conductive layer has greater thickness and lower resistivity than the second conductive layer. This local variation in quality optimizes current flow in different regions, reducing overall series resistance while keeping the structure manufacturable.
3Reliability
If standard conductive layers are used, then manufacturing is easier, but the quality factor is insufficient for high-performance resonant circuits
Solution Approach 1:
The patent modifies key parameters of the conductive layers, specifically increasing the thickness of the first conductive layer and selecting materials with lower resistivity. These parameter changes improve the quality factor by reducing series resistance while remaining compatible with extended IC manufacturing capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces series resistance by approximately one order of magnitude, leading to improved battery life and increased quality factor in resonant circuits, making it suitable for portable applications.
Implementation Method 1
A technique for reducing series resistance of an inductor system, which may increase the quality factor of the inductor system
Implementation Method 2
The at least one second conductive finger is interdigitated with the at least one first conductive finger without directly contacting the at least one first conductive finger
Implementation Method 3
The apparatus may include at least one first conductive via coupled to a second conductive layer and coupled the at least one first conductive finger, respectively
Data Source
AI summary
A technique for reducing series resistance of an inductor system, which may increase the quality factor of the inductor system, has been disclosed. An apparatus includes a conductive loop formed from a first conductive layer. The conductive loop comprises a first terminal and a second terminal. The first terminal includes at least one first conductive finger in the first conductive layer. The second terminal includes at least one second conductive finger in the first conductive layer. The at least one second conductive finger is interdigitated with the at least one first conductive finger without directly contacting the at least one first conductive finger. The apparatus may include a serpentine gap in the first conductive layer. The apparatus may include at least one first conductive via coupled to a second conductive layer and coupled the at least one first conductive fingers, respectively.