Interdigitated Isolation Devices for 3D NAND Memory Area Reduction
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently isolating high voltage operations from low voltage components while minimizing the area occupied by isolation devices, leading to potential leakage current issues.
Innovation Solution
The implementation of narrow active areas with interdigitated gates and a common gate structure, where the isolation devices are positioned next to each other, allowing for reduced footprint and shared gate biasing, coupled with optimized gate dielectric thickness to manage high and low voltage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional isolation devices are used to separate high voltage and low voltage components, then voltage isolation is achieved, but the area occupied by isolation devices increases
Solution Approach 1:
The patent combines multiple isolation devices into a shared isolation structure. Specifically, a first isolation device and a second isolation device share a common first well and a common second well, allowing them to be merged into a single integrated isolation unit. This merging reduces the total area occupied by isolation devices while maintaining the voltage isolation function between high voltage and low voltage components.
Solution Approach 2:
The shared wells serve multiple functions simultaneously. The common first well and common second well act as isolation structures for both the first isolation device and the second isolation device, providing universal isolation functionality. This multi-functionality allows the isolation structure to serve multiple purposes without requiring separate dedicated structures for each isolation device.
2Area of stationary object
If isolation devices are placed close together to reduce area, then footprint is reduced, but leakage current between adjacent devices increases
Solution Approach 1:
The shared wells act as intermediary structures between adjacent isolation devices. The common first well and common second well serve as mediating elements that physically separate the first isolation device and the second isolation device while allowing them to share the same isolation structure. This intermediary well structure prevents direct electrical contact between adjacent devices, thereby reducing leakage current while maintaining compact footprint.
3Ease of operation
If separate gate structures are used for each isolation device, then device control is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the gate structures of multiple isolation devices into a shared configuration. The first isolation device and the second isolation device share common wells and can utilize shared gate structures, reducing the total number of discrete gate components. This merging simplifies the overall device architecture while maintaining the ability to control each isolation device independently through appropriate biasing schemes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively isolates high voltage operations from low voltage components, reduces the area occupied by isolation devices, and minimizes leakage current risks, enhancing the efficiency and reliability of semiconductor devices.
Implementation Method 1
a gate dielectric material between the gate and the narrow active area
Data Source
AI summary
High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.