3D Interdigitated MIM Capacitor Layout for BEOL Capacitance Density
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Solution Overview
Problem
Current MIMCAP fabrication methods, especially for vertical structures, are complex and require numerous processing steps, hindering capacitance density increase and yield improvement due to their non-integrability into conventional BEOL processes.
Innovation Solution
A method for forming a 3D vertically stacked interdigitated MIMCAP structure with interdigitated electrodes and connecting vias within single unitary bodies, separated by a high-k insulating layer, using a reduced number of processing steps (five lithography and five etching steps), increasing the aspect ratio of electrodes to enhance capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional stacking methods with multiple MIMCAP layers are used, then capacitance density can be increased, but the number of lithography and etching steps increases significantly
Solution Approach 1:
The patent merges multiple MIMCAP layers into a single integrated structure where multiple capacitor units share common electrodes and insulating layers. This consolidation reduces the total number of lithography and etching steps while maintaining high capacitance density through the stacked configuration.
Solution Approach 2:
The patent creates universal electrode structures that serve multiple functions across different capacitor units. The same electrode layers are shared by adjacent capacitors, reducing the need for separate processing steps for each capacitor and simplifying the overall fabrication process.
2Quantity of substance
If vertical MIMCAP structures are implemented, then capacitance density increases, but extra processing steps are required that are not easily integrable into conventional BEOL processes
Solution Approach 1:
The patent segments the vertical MIMCAP structure into modular units that can be systematically integrated into conventional BEOL processes. By dividing the capacitor array into repeating patterns of electrodes and insulating layers, the fabrication can follow standard back-end-of-line processing sequences.
Solution Approach 2:
The patent transitions from planar capacitor layouts to vertical stacking in the third dimension. This dimensional change increases capacitance density without requiring additional lateral space, allowing integration into existing BEOL process flows that operate in the horizontal plane.
3Device complexity
If the number of processing steps is reduced, then fabrication complexity decreases, but achieving high capacitance density becomes more difficult
Solution Approach 1:
The patent employs a nested structure where multiple capacitor units are contained within a single fabrication sequence. By nesting capacitor units sharing common electrodes and insulating layers, the design achieves high capacitance density with fewer independent processing steps, as each nested unit contributes to the total capacitance without requiring separate fabrication cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, increases capacitance density, and improves yield by reducing complexity while maintaining a minimal horizontal footprint, potentially tripling total capacitance with a 2:1 aspect ratio.
Implementation Method 1
conformally depositing an insulating layer above the first conductive material for electrically separating the first set of interdigitated electrodes and the first metal plate
Implementation Method 2
depositing a first conductive material above the first dielectric layer, the first conductive material filling the first set of connecting vias
Data Source
AI summary
Forming a vertically stacked interdigitated metal-insulator-metal capacitor includes forming a first set of connecting vias within a first dielectric layer disposed above a semiconductor substrate followed by deposition of a first conductive material above the first dielectric layer, the first conductive material fills the first set of connecting vias. A top portion of the first conductive material is patterned to form a first set of interdigitated electrodes. A remaining portion of the first conductive material below the first set of interdigitated electrodes includes a first metal plate. An insulating layer is conformally deposited above the first conductive material for electrically separating the first set of interdigitated electrodes and the first metal plate.