Interdigitated Mold Layout for Higher-Density Semiconductor Packages

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Solution Overview

Problem

Conventional semiconductor packages face challenges in reducing costs and increasing density, particularly for low-cost leaded packages like SOT, SOP, and SOIC, where leadframe density and mold compound design limit the number of units that can be packed in a given area without increasing individual package size or tightening lead spacing.

Innovation Solution

The implementation of an interdigitated leadframe (IDLF) with offset lead positions and an interdigitated mold arrangement, featuring alternating extended and recessed mold regions, allows for higher leadframe density and reduced lead length, maintaining the same package footprint while increasing unit density by up to 33% for SOIC packages and 30-50% for SOT packages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional mold compound design with smooth sides is used, then manufacturing is simplified, but package unit density is limited

Engineering Contradiction:
Improvepackage unit densityVSAvoidmold compound shape complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The mold compound is divided into alternating extended and recessed regions along the leads, creating a segmented interdigitated pattern. This segmentation allows adjacent package units to be positioned closer together while maintaining adequate lead spacing, thereby increasing package unit density without requiring tighter lead spacing within each individual package.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The mold compound shape transitions from a conventional symmetric smooth-sided design to an asymmetric interdigitated pattern with alternating extended and recessed regions. This asymmetric design optimizes the use of available space on the leadframe sheet, allowing higher density packaging while maintaining manufacturing feasibility through standard molding processes.

Inventive Principle:
Principle #4Asymmetry

2Productivity

If leadframe density is increased through IDLF, then more units fit in given area, but lead length reduction may tighten lead spacing requirements

Engineering Contradiction:
Improveleadframe densityVSAvoidlead spacing requirement
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The mold compound extends laterally over the leads in alternating regions, utilizing the lateral dimension rather than only the vertical dimension. This lateral extension provides creepage distance and electrical isolation without requiring increased vertical spacing between leads, thus maintaining leadframe density while addressing spacing requirements through a different dimensional approach.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If extended mold regions are positioned over leads, then creepage distance is enhanced, but mold compound volume increases

Engineering Contradiction:
Improvecreepage distanceVSAvoidmold compound volume
Core Design Contradiction:
ReliabilityVSVolume of stationary object

Solution Approach 1:

The mold compound is provided in extended regions only where needed over the leads to provide creepage distance and ESD protection, while recessed regions are provided between adjacent leads where full coverage is not required. This local quality approach ensures reliability where critical while minimizing overall mold compound volume and material usage.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11942384B2Semiconductor package having an interdigitated mold arrangement
Publication Date: 2024.03.26 TEXAS INSTRUMENTS INC
  • US11942384B2 patent drawing
  • US11942384B2 patent drawing
  • US11942384B2 patent drawing

AI summary

A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.