Inter-Digitated Package Vias and Leads for Low-Inductance Memory I/O
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Solution Overview
Problem
Inductive effects in memory sub-systems, such as SSDs, lead to voltage drops during high-speed transitions, causing device resets or data corruption, and existing mitigation techniques increase power consumption and component size.
Innovation Solution
Implementing an inter-digitated pin arrangement on integrated circuit packages, where power and ground pins/vias are alternately arranged in a checkerboard pattern, to reduce mutual inductance and voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional pin arrangements are used in memory sub-systems, then device complexity is reduced and ease of manufacture is improved, but inductive effects cause voltage drops during high-speed transitions leading to device resets or data corruption
Solution Approach 1:
The patent applies asymmetry by arranging power pins and ground pins in a non-uniform, inter-digitated pattern rather than a traditional uniform grid. This asymmetric arrangement optimizes the electromagnetic field distribution to minimize mutual inductance between adjacent pins, thereby reducing voltage drops during high-speed transitions while maintaining manufacturing feasibility
Solution Approach 2:
The patent introduces ground pins as intermediary elements positioned between power pins in an inter-digitated pattern. These ground pins act as mediators that shield power pins from each other, reducing mutual inductance effects. The ground pins serve as electromagnetic shields that prevent direct coupling between adjacent power pins, thereby stabilizing voltage during high-speed transitions
2Reliability
If existing mitigation techniques for inductive effects are implemented, then voltage stability is improved, but power consumption increases and component size increases
Solution Approach 1:
The patent converts the harmful inductive coupling effect into a beneficial arrangement by intentionally designing the inter-digitated pin pattern. Instead of trying to eliminate inductance through power-consuming mitigation techniques, the design uses the natural electromagnetic field distribution created by alternating power and ground pins to reduce mutual inductance. This approach stabilizes voltage without requiring additional power consumption or larger components
3Reliability
If existing mitigation techniques for inductive effects are implemented, then voltage stability is improved, but component size increases
Solution Approach 1:
The patent applies local quality by optimizing the pin arrangement in specific local regions rather than uniformly across the entire package. The inter-digitated pattern concentrates ground pins strategically between power pins in high-inductance areas, providing localized electromagnetic shielding where it is most needed. This approach reduces voltage drops without requiring a uniform increase in package size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The inter-digitated arrangement reduces effective inductance by 22%, leading to a 22% increase in performance bandwidth and minimizing voltage drops at components.
Implementation Method 1
Inductive effects in memory sub-systems, such as SSDs, lead to voltage drops during high-speed transitions... the inter-digitated arrangement reduces effective inductance by 22%
Data Source
AI summary
Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).