Inter-Digitated Via and Lead Layout for Low-Inductance Memory Packages
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Solution Overview
Problem
Inductive effects in memory sub-systems, such as SSDs, cause voltage drops and data corruption during fast transitions, which existing shielding or buffering techniques fail to adequately address without increasing cost, size, or delay.
Innovation Solution
Implementing an inter-digitated arrangement of power and ground vias and leads in a checkerboard pattern to reduce mutual inductance, using the principle that currents flowing in opposite directions reduce mutual inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional shielding or buffering techniques are used to address inductive effects, then voltage drops and data corruption are reduced, but device complexity, cost, and size increase
Solution Approach 1:
Instead of adding external shielding or buffering components to reduce inductance, the patent inverts the approach by carefully arranging the existing power and ground leads in an inter-digitated pattern. This reverses the conventional wisdom that more shielding is needed, and instead uses the inherent properties of the lead arrangement itself to reduce mutual inductance, thereby reducing device complexity while maintaining reliability
Solution Approach 2:
The patent changes the spatial arrangement parameter of the power and ground leads from traditional grouped configurations to an inter-digitated alternating pattern. This parameter change in lead positioning modifies the magnetic coupling between adjacent leads, reducing mutual inductance without requiring additional shielding materials or buffering components, thus improving voltage stability without increasing device complexity
2Reliability
If power and ground leads are arranged in traditional configurations, then manufacturing is simpler, but mutual inductance causes voltage drops during fast transitions
Solution Approach 1:
The patent modifies the spatial arrangement parameter of the leads by implementing an inter-digitated pattern where power and ground leads alternate positions. This parameter change in lead positioning reduces mutual inductance between adjacent leads during fast transitions, improving voltage stability. The technique can be implemented through standard PCB routing or package design processes, maintaining ease of manufacture while achieving superior electrical performance
3Productivity
If lead length is increased to accommodate traditional arrangements, then manufacturing is easier, but inductance increases causing performance degradation
Solution Approach 1:
Rather than accepting that longer leads are needed for traditional arrangements, the patent inverts the approach by using an inter-digitated pattern that reduces inductance per unit length. This reversal of conventional lead arrangement methodology decreases the effective inductance of the power delivery path, thereby increasing performance bandwidth without requiring excessive via complexity
Solution Approach 2:
The patent applies local quality optimization by arranging power and ground leads in alternating pairs along their length. This local inter-digitated arrangement ensures that each segment of the lead path has minimized mutual inductance, creating uniformly low inductance characteristics throughout the entire power delivery network, which enhances overall productivity and performance bandwidth
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces effective inductance by 22%, leading to a 22% increase in performance bandwidth and minimizing voltage drops across components.
Implementation Method 1
the principle that currents flowing in opposite directions reduce mutual inductance
Data Source
AI summary
Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).