Interface Circuit Bias Compensation for Constant Signal Delay

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Semiconductor devices face challenges in maintaining constant signal delay times due to variations in supply voltage, leading to increased noise and reduced sensing characteristics.

Innovation Solution

An interface circuit with a buffer circuit and a bias generation circuit that adjusts the bias control voltage based on the supply voltage level, using a series connection of transistors and resistors to maintain constant delay times across varying power supply voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the supply voltage level varies, then the buffer circuit can operate with different power levels, but the delay time of the output signal becomes non-constant leading to increased noise and reduced sensing characteristics

Engineering Contradiction:
Improvepower supply voltage rangeVSAvoiddelay time consistency
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The bias generation circuit monitors the supply voltage level and automatically adjusts the bias control voltage in response to supply voltage variations. This feedback mechanism ensures that the buffer circuit maintains a constant delay time regardless of supply voltage changes, thereby resolving the contradiction between adaptability to different power levels and reliability of delay time consistency.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the parameter of bias control voltage to compensate for supply voltage variations. By dynamically adjusting the bias control voltage based on the detected supply voltage level, the system maintains constant delay time while adapting to different power supply conditions, thus resolving the contradiction between versatility and reliability.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the delay time is kept constant through bias adjustment, then sensing characteristics are improved, but the circuit complexity increases due to the bias generation circuit

Engineering Contradiction:
Improvesensing characteristicsVSAvoidcircuit structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The bias generation circuit serves multiple functions: it monitors supply voltage, generates appropriate bias control voltage, and compensates for voltage variations. By consolidating these functions into a single integrated circuit, the patent minimizes the increase in overall system complexity while achieving improved sensing characteristics through constant delay time.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If the bias control voltage is adjusted to compensate for supply voltage changes, then delay time consistency is maintained, but the power consumption may increase

Engineering Contradiction:
Improvedelay time stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The bias generation circuit dynamically adjusts the bias control voltage only when supply voltage variations are detected. This dynamic operation ensures that power consumption is optimized by making adjustments only when necessary to maintain delay time stability, rather than continuously consuming additional power.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11804841B2Interface circuit and operating method thereof to compensate for supply voltage variations
Publication Date: 2023.10.31 SAMSUNG ELECTRONICS CO LTD
  • US11804841B2 patent drawing
  • US11804841B2 patent drawing
  • US11804841B2 patent drawing

AI summary

An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.