Semiconductor Interface Board for Exposed Die Signal Probing

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Solution Overview

Problem

The challenge in semiconductor device testing is the difficulty in directly accessing and analyzing internal signals of semiconductor dies due to the configuration of the board and die, which obscures the die and prevents probes from making direct contact, and the risk of damaging the die during testing due to long cable connections and direct contact with the chuck connector.

Innovation Solution

The interface structure includes an interface board with through board vias and connectors that allow for direct electrical coupling between the semiconductor die and the test equipment, with the die being exposed for probe contact and the chuck connector contacting the board instead of the die, reducing the risk of damage and enabling high-frequency analysis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the die is directly contacted by probes during testing, then internal signal analysis can be performed, but the die may be damaged due to direct contact with the chuck connector and long cable connections

Engineering Contradiction:
Improveinternal signal analysis capabilityVSAvoiddie damage risk
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an interface board as an intermediary component between the die and the chuck connector. The interface board includes a test pattern layer with test pads that electrically connect to the die through wire bonds, while connecting to the chuck connector through lower connectors. This intermediary structure allows probe contact with test pads instead of directly with the die, reducing the risk of die damage while enabling internal signal analysis.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the die is exposed for direct probe contact, then internal signals can be accessed, but the board and die configuration currently obscures the die and prevents direct contact

Engineering Contradiction:
Improveprobe access to internal signalsVSAvoidboard and die configuration
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent segments the testing system into distinct functional layers: the die layer, the interface board layer with test pattern, and the chuck connector layer. The interface board is configured with through-board vias that create separate electrical pathways - one set connecting upper connectors to the die through wire bonds, and another set connecting lower connectors to the chuck. This segmentation allows probes to access test pads on the interface board without needing to directly contact the die, while maintaining all necessary electrical connections.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If long cable connections are used during testing, then the die can be connected to test equipment, but the risk of damaging the die increases

Engineering Contradiction:
Improveconnection to test equipmentVSAvoiddie damage risk from cable connections
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the vulnerable die from the direct connection path to the chuck connector. Instead of connecting the die directly to the chuck connector through long cables, the interface board is positioned between them. The lower connectors on the interface board make contact with the chuck connector, while the die connects to the interface board through shorter, more controlled wire bonds. This extraction of the die from the direct connection path reduces mechanical stress and damage risk from cable movements and connector contact forces.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12181518B2Semiconductor device with interface structure
Publication Date: 2024.12.31 NAN YA TECH
  • US12181518B2 patent drawing
  • US12181518B2 patent drawing
  • US12181518B2 patent drawing

AI summary

The present application discloses a semiconductor device with an interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment.